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!fixup use PoisonGeneratingMetadataIDs.
1 parent ca701a1 commit da0a211

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3 files changed

+26
-39
lines changed

3 files changed

+26
-39
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp

Lines changed: 4 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1060,25 +1060,10 @@ Instruction *InstCombinerImpl::visitLoadInst(LoadInst &LI) {
10601060
V1->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
10611061
V2->setAlignment(Alignment);
10621062
V2->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
1063-
// Can copy any metadata that cannot trigger UB. In particular do not
1064-
// copy !noundef or !invariant.load.
1065-
unsigned SafeMDKinds[] = {LLVMContext::MD_dbg,
1066-
LLVMContext::MD_tbaa,
1067-
LLVMContext::MD_prof,
1068-
LLVMContext::MD_fpmath,
1069-
LLVMContext::MD_tbaa_struct,
1070-
LLVMContext::MD_alias_scope,
1071-
LLVMContext::MD_noalias,
1072-
LLVMContext::MD_nontemporal,
1073-
LLVMContext::MD_mem_parallel_loop_access,
1074-
LLVMContext::MD_access_group,
1075-
LLVMContext::MD_nonnull,
1076-
LLVMContext::MD_align,
1077-
LLVMContext::MD_dereferenceable,
1078-
LLVMContext::MD_dereferenceable_or_null,
1079-
LLVMContext::MD_range};
1080-
V1->copyMetadata(LI, SafeMDKinds);
1081-
V2->copyMetadata(LI, SafeMDKinds);
1063+
// It is safe to copy any metadata that does not trigger UB. Copy any
1064+
// poison-generating metadata.
1065+
V1->copyMetadata(LI, Instruction::PoisonGeneratingMetadataIDs);
1066+
V2->copyMetadata(LI, Instruction::PoisonGeneratingMetadataIDs);
10821067
return SelectInst::Create(SI->getCondition(), V1, V2);
10831068
}
10841069

‎llvm/test/Transforms/InstCombine/loadstore-metadata.ll

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,8 @@ entry:
190190
define ptr @preserve_load_metadata_after_select_transform1(i1 %c, ptr dereferenceable(8) %a, ptr dereferenceable(8) %b) {
191191
; CHECK-LABEL: @preserve_load_metadata_after_select_transform1(
192192
; CHECK-NEXT: entry:
193-
; CHECK-NEXT: [[B_VAL:%.*]] = load ptr, ptr [[B:%.*]], align 1, !tbaa [[TBAA0]], !dereferenceable [[META8]], !llvm.access.group [[META6]]
194-
; CHECK-NEXT: [[A_VAL:%.*]] = load ptr, ptr [[A:%.*]], align 1, !tbaa [[TBAA0]], !dereferenceable [[META8]], !llvm.access.group [[META6]]
193+
; CHECK-NEXT: [[B_VAL:%.*]] = load ptr, ptr [[B:%.*]], align 1, !nonnull [[META6]], !align [[META8]]
194+
; CHECK-NEXT: [[A_VAL:%.*]] = load ptr, ptr [[A:%.*]], align 1, !nonnull [[META6]], !align [[META8]]
195195
; CHECK-NEXT: [[L_SEL:%.*]] = select i1 [[C:%.*]], ptr [[B_VAL]], ptr [[A_VAL]]
196196
; CHECK-NEXT: ret ptr [[L_SEL]]
197197
;
@@ -205,8 +205,8 @@ entry:
205205
define i32 @preserve_load_metadata_after_select_transform_range(i1 %c, ptr dereferenceable(8) %a, ptr dereferenceable(8) %b) {
206206
; CHECK-LABEL: @preserve_load_metadata_after_select_transform_range(
207207
; CHECK-NEXT: entry:
208-
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B:%.*]], align 1
209-
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A:%.*]], align 1
208+
; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B:%.*]], align 1, !range [[RNG10:![0-9]+]]
209+
; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A:%.*]], align 1, !range [[RNG10]]
210210
; CHECK-NEXT: [[L_SEL:%.*]] = select i1 [[C:%.*]], i32 [[B_VAL]], i32 [[A_VAL]]
211211
; CHECK-NEXT: ret i32 [[L_SEL]]
212212
;
@@ -294,7 +294,7 @@ define double @preserve_load_metadata_after_select_transform_metadata_missing_4(
294294
; CHECK-LABEL: @preserve_load_metadata_after_select_transform_metadata_missing_4(
295295
; CHECK-NEXT: entry:
296296
; CHECK-NEXT: [[L_A:%.*]] = load double, ptr [[A:%.*]], align 8, !tbaa [[TBAA0]], !alias.scope [[META3]], !noalias [[META3]], !llvm.access.group [[META6]]
297-
; CHECK-NEXT: [[L_B:%.*]] = load double, ptr [[B:%.*]], align 8, !tbaa [[TBAA0]], !alias.scope [[META10:![0-9]+]], !noalias [[META10]], !llvm.access.group [[ACC_GRP13:![0-9]+]]
297+
; CHECK-NEXT: [[L_B:%.*]] = load double, ptr [[B:%.*]], align 8, !tbaa [[TBAA0]], !alias.scope [[META11:![0-9]+]], !noalias [[META11]], !llvm.access.group [[ACC_GRP14:![0-9]+]]
298298
; CHECK-NEXT: [[CMP_I:%.*]] = fcmp fast olt double [[L_A]], [[L_B]]
299299
; CHECK-NEXT: [[L_SEL:%.*]] = select i1 [[CMP_I]], double [[L_B]], double [[L_A]]
300300
; CHECK-NEXT: ret double [[L_SEL]]
@@ -337,8 +337,9 @@ entry:
337337
; CHECK: [[META7]] = !{i32 1}
338338
; CHECK: [[META8]] = !{i64 8}
339339
; CHECK: [[ACC_GRP9]] = distinct !{}
340-
; CHECK: [[META10]] = !{[[META11:![0-9]+]]}
341-
; CHECK: [[META11]] = distinct !{[[META11]], [[META12:![0-9]+]]}
342-
; CHECK: [[META12]] = distinct !{[[META12]]}
343-
; CHECK: [[ACC_GRP13]] = distinct !{}
340+
; CHECK: [[RNG10]] = !{i32 0, i32 42}
341+
; CHECK: [[META11]] = !{[[META12:![0-9]+]]}
342+
; CHECK: [[META12]] = distinct !{[[META12]], [[META13:![0-9]+]]}
343+
; CHECK: [[META13]] = distinct !{[[META13]]}
344+
; CHECK: [[ACC_GRP14]] = distinct !{}
344345
;.

‎llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
55
target triple = "x86_64-unknown-linux-gnu"
66

7+
; FIXME: !llvm.access.group should be preserved, loop should be vectorized.
78
; End-to-end test for https://github.com/llvm/llvm-project/issues/115595.
89
define void @test(i32 noundef %nface, i32 noundef %ncell, ptr noalias noundef %face_cell, ptr noalias noundef %x, ptr noalias noundef %y) #0 {
910
; CHECK-LABEL: define void @test(
@@ -14,16 +15,16 @@ define void @test(i32 noundef %nface, i32 noundef %ncell, ptr noalias noundef %f
1415
; CHECK: [[FOR_BODY_PREHEADER]]:
1516
; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[NFACE]] to i64
1617
; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr inbounds nuw i32, ptr [[FACE_CELL]], i64 [[TMP0]]
17-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[NFACE]], 4
18-
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[FOR_BODY_PREHEADER14:.*]], label %[[VECTOR_PH:.*]]
18+
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NFACE]], 4
19+
; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_BODY_PREHEADER14:.*]], label %[[VECTOR_PH:.*]]
1920
; CHECK: [[VECTOR_PH]]:
20-
; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 2147483644
21+
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[TMP0]], 2147483644
2122
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
2223
; CHECK: [[VECTOR_BODY]]:
23-
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
24-
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds nuw i32, ptr [[FACE_CELL]], i64 [[INDEX]]
25-
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]], !llvm.access.group [[ACC_GRP4:![0-9]+]]
26-
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i32, ptr [[INVARIANT_GEP]], i64 [[INDEX]]
24+
; CHECK-NEXT: [[INDVARS_IV_EPIL:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
25+
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw i32, ptr [[FACE_CELL]], i64 [[INDVARS_IV_EPIL]]
26+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4, !tbaa [[TBAA0:![0-9]+]], !llvm.access.group [[ACC_GRP4:![0-9]+]]
27+
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i32, ptr [[INVARIANT_GEP]], i64 [[INDVARS_IV_EPIL]]
2728
; CHECK-NEXT: [[WIDE_LOAD12:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4, !tbaa [[TBAA0]], !llvm.access.group [[ACC_GRP4]]
2829
; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i32> [[WIDE_LOAD]] to <4 x i64>
2930
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds double, ptr [[Y]], <4 x i64> [[TMP3]]
@@ -34,14 +35,14 @@ define void @test(i32 noundef %nface, i32 noundef %ncell, ptr noalias noundef %f
3435
; CHECK-NEXT: [[TMP7:%.*]] = fcmp fast olt <4 x double> [[WIDE_MASKED_GATHER]], [[WIDE_MASKED_GATHER13]]
3536
; CHECK-NEXT: [[TMP8:%.*]] = select <4 x i1> [[TMP7]], <4 x double> [[WIDE_MASKED_GATHER13]], <4 x double> [[WIDE_MASKED_GATHER]]
3637
; CHECK-NEXT: tail call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> [[TMP8]], <4 x ptr> [[TMP4]], i32 8, <4 x i1> splat (i1 true)), !tbaa [[TBAA5]], !llvm.access.group [[ACC_GRP4]]
37-
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
38-
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
38+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDVARS_IV_EPIL]], 4
39+
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[UNROLL_ITER]]
3940
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
4041
; CHECK: [[MIDDLE_BLOCK]]:
41-
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[TMP0]]
42+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UNROLL_ITER]], [[TMP0]]
4243
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY_PREHEADER14]]
4344
; CHECK: [[FOR_BODY_PREHEADER14]]:
44-
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[N_VEC]], %[[MIDDLE_BLOCK]] ]
45+
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[UNROLL_ITER]], %[[MIDDLE_BLOCK]] ]
4546
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
4647
; CHECK: [[FOR_COND_CLEANUP]]:
4748
; CHECK-NEXT: ret void

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