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[AArch64] Add support for the Branch Record Buffer extension
This introduces asm support for the Branch Record Buffer extension, through the new 'brbe' subtarget feature. It consists of a new set of system registers that enable the handling of branch records. Patch written by Simon Tatham. Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D92389
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‎llvm/include/llvm/Support/AArch64TargetParser.def

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@@ -107,6 +107,7 @@ AARCH64_ARCH_EXT_NAME("f32mm", AArch64::AEK_F32MM, "+f32mm", "-f32m
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AARCH64_ARCH_EXT_NAME("f64mm", AArch64::AEK_F64MM, "+f64mm", "-f64mm")
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AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme")
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AARCH64_ARCH_EXT_NAME("ls64", AArch64::AEK_LS64, "+ls64", "-ls64")
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AARCH64_ARCH_EXT_NAME("brbe", AArch64::AEK_BRBE, "+brbe", "-brbe")
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#undef AARCH64_ARCH_EXT_NAME
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#ifndef AARCH64_CPU_NAME

‎llvm/include/llvm/Support/AArch64TargetParser.h

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@@ -63,6 +63,7 @@ enum ArchExtKind : uint64_t {
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AEK_F32MM = 1ULL << 31,
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AEK_F64MM = 1ULL << 32,
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AEK_LS64 = 1ULL << 33,
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AEK_BRBE = 1ULL << 34,
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};
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enum class ArchKind {

‎llvm/lib/Support/AArch64TargetParser.cpp

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@@ -100,6 +100,8 @@ bool AArch64::getExtensionFeatures(uint64_t Extensions,
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Features.push_back("+sve2-bitperm");
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if (Extensions & AEK_RCPC)
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Features.push_back("+rcpc");
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if (Extensions & AEK_BRBE)
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Features.push_back("+brbe");
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return true;
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}

‎llvm/lib/Target/AArch64/AArch64.td

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@@ -412,6 +412,9 @@ def FeatureHCX : SubtargetFeature<
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def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
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"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
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415+
def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
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"true", "Enable Branch Record Buffer Extension">;
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def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
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"true", "Enable fine grained virtualization traps extension">;
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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@@ -157,6 +157,8 @@ def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
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AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
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def HasLS64 : Predicate<"Subtarget->hasLS64()">,
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AssemblerPredicate<(all_of FeatureLS64), "ls64">;
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def HasBRBE : Predicate<"Subtarget->hasBRBE()">,
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AssemblerPredicate<(all_of FeatureBRBE), "brbe">;
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def IsLE : Predicate<"Subtarget->isLittleEndian()">;
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def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
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def IsWindows : Predicate<"Subtarget->isTargetWindows()">;

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

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@@ -184,6 +184,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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// Future architecture extensions.
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bool HasETE = false;
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bool HasTRBE = false;
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bool HasBRBE = false;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove = false;

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td

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@@ -1574,6 +1574,25 @@ def : RWSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
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let Requires = [{ {AArch64::FeatureLS64} }] in
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def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;
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1577+
// Branch Record Buffer system registers
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let Requires = [{ {AArch64::FeatureBRBE} }] in {
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def : RWSysReg<"BRBCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b000>;
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def : RWSysReg<"BRBCR_EL12", 0b10, 0b101, 0b1001, 0b0000, 0b000>;
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def : RWSysReg<"BRBCR_EL2", 0b10, 0b100, 0b1001, 0b0000, 0b000>;
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def : RWSysReg<"BRBFCR_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b001>;
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def : ROSysReg<"BRBIDR0_EL1", 0b10, 0b001, 0b1001, 0b0010, 0b000>;
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def : RWSysReg<"BRBINFINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b000>;
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def : RWSysReg<"BRBSRCINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b001>;
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def : RWSysReg<"BRBTGTINJ_EL1", 0b10, 0b001, 0b1001, 0b0001, 0b010>;
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def : RWSysReg<"BRBTS_EL1", 0b10, 0b001, 0b1001, 0b0000, 0b010>;
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foreach n = 0-31 in {
1589+
defvar nb = !cast<bits<5>>(n);
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def : ROSysReg<"BRBINF"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b00}>;
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def : ROSysReg<"BRBSRC"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b01}>;
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def : ROSysReg<"BRBTGT"#n#"_EL1", 0b10, 0b001, 0b1000, nb{3-0}, {nb{4},0b10}>;
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}
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}
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// Cyclone specific system registers
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// Op0 Op1 CRn CRm Op2
15791598
let Requires = [{ {AArch64::ProcAppleA7} }] in

‎llvm/test/MC/AArch64/brbe.s

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// RUN: not llvm-mc -triple aarch64 -mattr +brbe -show-encoding %s 2>%t | FileCheck %s
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// RUN: FileCheck --check-prefix=ERROR %s < %t
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// RUN: not llvm-mc -triple aarch64 -show-encoding %s 2>%t
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// RUN: FileCheck --check-prefix=ERROR-NO-BRBE %s < %t
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6+
msr BRBCR_EL1, x0
7+
mrs x1, BRBCR_EL1
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// CHECK: msr BRBCR_EL1, x0 // encoding: [0x00,0x90,0x11,0xd5]
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// CHECK: mrs x1, BRBCR_EL1 // encoding: [0x01,0x90,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
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msr BRBCR_EL12, x2
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mrs x3, BRBCR_EL12
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// CHECK: msr BRBCR_EL12, x2 // encoding: [0x02,0x90,0x15,0xd5]
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// CHECK: mrs x3, BRBCR_EL12 // encoding: [0x03,0x90,0x35,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
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msr BRBCR_EL2, x4
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mrs x5, BRBCR_EL2
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// CHECK: msr BRBCR_EL2, x4 // encoding: [0x04,0x90,0x14,0xd5]
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// CHECK: mrs x5, BRBCR_EL2 // encoding: [0x05,0x90,0x34,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
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msr BRBFCR_EL1, x6
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mrs x7, BRBFCR_EL1
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// CHECK: msr BRBFCR_EL1, x6 // encoding: [0x26,0x90,0x11,0xd5]
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// CHECK: mrs x7, BRBFCR_EL1 // encoding: [0x27,0x90,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
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msr BRBIDR0_EL1, x8
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mrs x9, BRBIDR0_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x9, BRBIDR0_EL1 // encoding: [0x09,0x92,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
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msr BRBINFINJ_EL1, x10
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mrs x11, BRBINFINJ_EL1
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// CHECK: msr BRBINFINJ_EL1, x10 // encoding: [0x0a,0x91,0x11,0xd5]
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// CHECK: mrs x11, BRBINFINJ_EL1 // encoding: [0x0b,0x91,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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msr BRBSRCINJ_EL1, x12
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mrs x13, BRBSRCINJ_EL1
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// CHECK: msr BRBSRCINJ_EL1, x12 // encoding: [0x2c,0x91,0x11,0xd5]
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// CHECK: mrs x13, BRBSRCINJ_EL1 // encoding: [0x2d,0x91,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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msr BRBTGTINJ_EL1, x14
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mrs x15, BRBTGTINJ_EL1
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// CHECK: msr BRBTGTINJ_EL1, x14 // encoding: [0x4e,0x91,0x11,0xd5]
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// CHECK: mrs x15, BRBTGTINJ_EL1 // encoding: [0x4f,0x91,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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msr BRBTS_EL1, x16
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mrs x17, BRBTS_EL1
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// CHECK: msr BRBTS_EL1, x16 // encoding: [0x50,0x90,0x11,0xd5]
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// CHECK: mrs x17, BRBTS_EL1 // encoding: [0x51,0x90,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
68+
69+
// Rather than testing all 32 registers in the three BRBINF/BRBSRC/BRBTGT
70+
// families, I'll test a representative sample, including all bits clear,
71+
// all bits set, each bit set individually, and a couple of intermediate
72+
// patterns.
73+
74+
msr BRBINF0_EL1, x18
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mrs x19, BRBINF0_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x19, BRBINF0_EL1 // encoding: [0x13,0x80,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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81+
msr BRBINF1_EL1, x20
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mrs x21, BRBINF1_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x21, BRBINF1_EL1 // encoding: [0x15,0x81,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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88+
msr BRBINF2_EL1, x22
89+
mrs x23, BRBINF2_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x23, BRBINF2_EL1 // encoding: [0x17,0x82,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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msr BRBSRC4_EL1, x24
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mrs x25, BRBSRC4_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x25, BRBSRC4_EL1 // encoding: [0x39,0x84,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
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msr BRBSRC8_EL1, x26
103+
mrs x27, BRBSRC8_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x27, BRBSRC8_EL1 // encoding: [0x3b,0x88,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
108+
109+
msr BRBSRC16_EL1, x28
110+
mrs x29, BRBSRC16_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x29, BRBSRC16_EL1 // encoding: [0xbd,0x80,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:10: error: expected readable system register
115+
116+
msr BRBTGT10_EL1, x0
117+
mrs x1, BRBTGT10_EL1
118+
// ERROR: [[@LINE-2]]:5: error: expected writable system register
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// CHECK: mrs x1, BRBTGT10_EL1 // encoding: [0x41,0x8a,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
121+
// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
122+
123+
msr BRBTGT21_EL1, x2
124+
mrs x3, BRBTGT21_EL1
125+
// ERROR: [[@LINE-2]]:5: error: expected writable system register
126+
// CHECK: mrs x3, BRBTGT21_EL1 // encoding: [0xc3,0x85,0x31,0xd5]
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// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
128+
// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
129+
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msr BRBTGT31_EL1, x4
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mrs x5, BRBTGT31_EL1
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// ERROR: [[@LINE-2]]:5: error: expected writable system register
133+
// CHECK: mrs x5, BRBTGT31_EL1 // encoding: [0xc5,0x8f,0x31,0xd5]
134+
// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
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// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register

‎llvm/test/MC/Disassembler/AArch64/brbe.txt

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# RUN: llvm-mc -triple=aarch64 -mattr=+brbe -disassemble %s 2> %t | FileCheck %s
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# RUN: llvm-mc -triple=aarch64 -disassemble %s 2> %t | FileCheck --check-prefix=NO-BRBE %s
3+
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[0x00,0x90,0x11,0xd5]
5+
[0x01,0x90,0x31,0xd5]
6+
# CHECK: msr BRBCR_EL1, x0
7+
# CHECK: mrs x1, BRBCR_EL1
8+
# NO-BRBE: msr S2_1_C9_C0_0, x0
9+
# NO-BRBE: mrs x1, S2_1_C9_C0_0
10+
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[0x02,0x90,0x15,0xd5]
12+
[0x03,0x90,0x35,0xd5]
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# CHECK: msr BRBCR_EL12, x2
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# CHECK: mrs x3, BRBCR_EL12
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# NO-BRBE: msr S2_5_C9_C0_0, x2
16+
# NO-BRBE: mrs x3, S2_5_C9_C0_0
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18+
[0x04,0x90,0x14,0xd5]
19+
[0x05,0x90,0x34,0xd5]
20+
# CHECK: msr BRBCR_EL2, x4
21+
# CHECK: mrs x5, BRBCR_EL2
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# NO-BRBE: msr S2_4_C9_C0_0, x4
23+
# NO-BRBE: mrs x5, S2_4_C9_C0_0
24+
25+
[0x26,0x90,0x11,0xd5]
26+
[0x27,0x90,0x31,0xd5]
27+
# CHECK: msr BRBFCR_EL1, x6
28+
# CHECK: mrs x7, BRBFCR_EL1
29+
# NO-BRBE: msr S2_1_C9_C0_1, x6
30+
# NO-BRBE: mrs x7, S2_1_C9_C0_1
31+
32+
[0x08,0x92,0x11,0xd5] # expect failure: BRBIDR0_EL1 is RO
33+
[0x09,0x92,0x31,0xd5]
34+
# CHECK: msr S2_1_C9_C2_0, x8
35+
# CHECK: mrs x9, BRBIDR0_EL1
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# NO-BRBE: msr S2_1_C9_C2_0, x8
37+
# NO-BRBE: mrs x9, S2_1_C9_C2_0
38+
39+
[0x0a,0x91,0x11,0xd5]
40+
[0x0b,0x91,0x31,0xd5]
41+
# CHECK: msr BRBINFINJ_EL1, x10
42+
# CHECK: mrs x11, BRBINFINJ_EL1
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# NO-BRBE: msr S2_1_C9_C1_0, x10
44+
# NO-BRBE: mrs x11, S2_1_C9_C1_0
45+
46+
[0x2c,0x91,0x11,0xd5]
47+
[0x2d,0x91,0x31,0xd5]
48+
# CHECK: msr BRBSRCINJ_EL1, x12
49+
# CHECK: mrs x13, BRBSRCINJ_EL1
50+
# NO-BRBE: msr S2_1_C9_C1_1, x12
51+
# NO-BRBE: mrs x13, S2_1_C9_C1_1
52+
53+
[0x4e,0x91,0x11,0xd5]
54+
[0x4f,0x91,0x31,0xd5]
55+
# CHECK: msr BRBTGTINJ_EL1, x14
56+
# CHECK: mrs x15, BRBTGTINJ_EL1
57+
# NO-BRBE: msr S2_1_C9_C1_2, x14
58+
# NO-BRBE: mrs x15, S2_1_C9_C1_2
59+
60+
[0x50,0x90,0x11,0xd5]
61+
[0x51,0x90,0x31,0xd5]
62+
# CHECK: msr BRBTS_EL1, x16
63+
# CHECK: mrs x17, BRBTS_EL1
64+
# NO-BRBE: msr S2_1_C9_C0_2, x16
65+
# NO-BRBE: mrs x17, S2_1_C9_C0_2
66+
67+
[0x12,0x80,0x11,0xd5] # expect failure: BRBINF0_EL1 is RO
68+
[0x13,0x80,0x31,0xd5]
69+
# CHECK: msr S2_1_C8_C0_0, x18
70+
# CHECK: mrs x19, BRBINF0_EL1
71+
# NO-BRBE: msr S2_1_C8_C0_0, x18
72+
# NO-BRBE: mrs x19, S2_1_C8_C0_0
73+
74+
[0x14,0x81,0x11,0xd5] # expect failure: BRBINF1_EL1 is RO
75+
[0x15,0x81,0x31,0xd5]
76+
# CHECK: msr S2_1_C8_C1_0, x20
77+
# CHECK: mrs x21, BRBINF1_EL1
78+
# NO-BRBE: msr S2_1_C8_C1_0, x20
79+
# NO-BRBE: mrs x21, S2_1_C8_C1_0
80+
81+
[0x16,0x82,0x11,0xd5] # expect failure: BRBINF2_EL1 is RO
82+
[0x17,0x82,0x31,0xd5]
83+
# CHECK: msr S2_1_C8_C2_0, x22
84+
# CHECK: mrs x23, BRBINF2_EL1
85+
# NO-BRBE: msr S2_1_C8_C2_0, x22
86+
# NO-BRBE: mrs x23, S2_1_C8_C2_0
87+
88+
[0x38,0x84,0x11,0xd5] # expect failure: BRBSRC4_EL1 is RO
89+
[0x39,0x84,0x31,0xd5]
90+
# CHECK: msr S2_1_C8_C4_1, x24
91+
# CHECK: mrs x25, BRBSRC4_EL1
92+
# NO-BRBE: msr S2_1_C8_C4_1, x24
93+
# NO-BRBE: mrs x25, S2_1_C8_C4_1
94+
95+
[0x3a,0x88,0x11,0xd5] # expect failure: BRBSRC8_EL1 is RO
96+
[0x3b,0x88,0x31,0xd5]
97+
# CHECK: msr S2_1_C8_C8_1, x26
98+
# CHECK: mrs x27, BRBSRC8_EL1
99+
# NO-BRBE: msr S2_1_C8_C8_1, x26
100+
# NO-BRBE: mrs x27, S2_1_C8_C8_1
101+
102+
[0xbc,0x80,0x11,0xd5] # expect failure: BRBSRC16_EL1 is RO
103+
[0xbd,0x80,0x31,0xd5]
104+
# CHECK: msr S2_1_C8_C0_5, x28
105+
# CHECK: mrs x29, BRBSRC16_EL1
106+
# NO-BRBE: msr S2_1_C8_C0_5, x28
107+
# NO-BRBE: mrs x29, S2_1_C8_C0_5
108+
109+
[0x40,0x8a,0x11,0xd5] # expect failure: BRBTGT10_EL1 is RO
110+
[0x41,0x8a,0x31,0xd5]
111+
# CHECK: msr S2_1_C8_C10_2, x0
112+
# CHECK: mrs x1, BRBTGT10_EL1
113+
# NO-BRBE: msr S2_1_C8_C10_2, x0
114+
# NO-BRBE: mrs x1, S2_1_C8_C10_2
115+
116+
[0xc2,0x85,0x11,0xd5] # expect failure: BRBTGT21_EL1 is RO
117+
[0xc3,0x85,0x31,0xd5]
118+
# CHECK: msr S2_1_C8_C5_6, x2
119+
# CHECK: mrs x3, BRBTGT21_EL1
120+
# NO-BRBE: msr S2_1_C8_C5_6, x2
121+
# NO-BRBE: mrs x3, S2_1_C8_C5_6
122+
123+
[0xc4,0x8f,0x11,0xd5] # expect failure: BRBTGT31_EL1 is RO
124+
[0xc5,0x8f,0x31,0xd5]
125+
# CHECK: msr S2_1_C8_C15_6, x4
126+
# CHECK: mrs x5, BRBTGT31_EL1
127+
# NO-BRBE: msr S2_1_C8_C15_6, x4
128+
# NO-BRBE: mrs x5, S2_1_C8_C15_6

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