Corrected slli-srli fusion - the immediate shift ammounts have to be the

same.

Author: mgudim

llvm/lib/Target/RISCV/RISCVFeatures.td

@@ -997,20 +997,13 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
                                    [TuneNoDefaultUnroll,
                                     TuneShortForwardBranchOpt]>;
 
-<<<<<<< HEAD
-def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
-                                         "Ventana-Veyron Series processors",
-                                         [TuneLUIADDIFusion]>;
-=======
 def TuneVeyronFusions : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron",
                                          "Ventana Veyron-Series processors",
                                          [TuneLUIADDIFusion,
                                           TuneAUIPCADDIFusion,
                                           TuneSLLISRLIFusion,
                                           TuneLDADDFusion]>;
 
->>>>>>> bbf0196a7d42 ([RISCV] Macro-fusion support for veyron-v1 CPU.)
-
 // Assume that lock-free native-width atomics are available, even if the target
 // and operating system combination would not usually provide them. The user
 // is responsible for providing any necessary __sync implementations. Code

llvm/lib/Target/RISCV/RISCVMacroFusion.cpp

@@ -88,7 +88,7 @@ static bool isSLLISRLI(const MachineInstr *FirstMI,
     return false;
 
   unsigned SLLIImm = FirstMI->getOperand(2).getImm();
-  if (IsShiftBy48 ? (SLLIImm != 48) : (SLLIImm > 32))
+  if (IsShiftBy48 ? (SLLIImm != 48) : (SLLIImm != 32))
     return false;
 
   return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);