Skip to content

Commit dade11f

Browse files
michaelmaitlandmichaelmaitland
authored
[RISCV] Bump Pointer Masking extension version (#96715)
These extensions had their version number bumped and still experimental (under public review). I didn't see anything in the [commit history](https://github.com/riscv/riscv-j-extension/commits/master/) since #79929 that would warrant a change to the implementation of pointer masking in the compiler.
1 parent a1bce0b commit dade11f

File tree

7 files changed

+58
-58
lines changed

7 files changed

+58
-58
lines changed

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1683,44 +1683,44 @@
16831683
// CHECK-ZICFISS-EXT: __riscv_zicfiss 4000{{$}}
16841684

16851685
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1686-
// RUN: -march=rv32i_ssnpm0p8 -E -dM %s \
1686+
// RUN: -march=rv32i_ssnpm1p0 -E -dM %s \
16871687
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
16881688
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1689-
// RUN: -march=rv64i_ssnpm0p8 -E -dM %s \
1689+
// RUN: -march=rv64i_ssnpm1p0 -E -dM %s \
16901690
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
1691-
// CHECK-SSNPM-EXT: __riscv_ssnpm 8000{{$}}
1691+
// CHECK-SSNPM-EXT: __riscv_ssnpm 1000000{{$}}
16921692

16931693
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1694-
// RUN: -march=rv32i_smnpm0p8 -E -dM %s \
1694+
// RUN: -march=rv32i_smnpm1p0 -E -dM %s \
16951695
// RUN: -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
16961696
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1697-
// RUN: -march=rv64i_smnpm0p8 -E -dM %s \
1697+
// RUN: -march=rv64i_smnpm1p0 -E -dM %s \
16981698
// RUN: -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
1699-
// CHECK-SMNPM-EXT: __riscv_smnpm 8000{{$}}
1699+
// CHECK-SMNPM-EXT: __riscv_smnpm 1000000{{$}}
17001700

17011701
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1702-
// RUN: -march=rv32i_smmpm0p8 -E -dM %s \
1702+
// RUN: -march=rv32i_smmpm1p0 -E -dM %s \
17031703
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
17041704
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1705-
// RUN: -march=rv64i_smmpm0p8 -E -dM %s \
1705+
// RUN: -march=rv64i_smmpm1p0 -E -dM %s \
17061706
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
1707-
// CHECK-SMMPM-EXT: __riscv_smmpm 8000{{$}}
1707+
// CHECK-SMMPM-EXT: __riscv_smmpm 1000000{{$}}
17081708

17091709
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1710-
// RUN: -march=rv32i_sspm0p8 -E -dM %s \
1710+
// RUN: -march=rv32i_sspm1p0 -E -dM %s \
17111711
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
17121712
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1713-
// RUN: -march=rv64i_sspm0p8 -E -dM %s \
1713+
// RUN: -march=rv64i_sspm1p0 -E -dM %s \
17141714
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
1715-
// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}
1715+
// CHECK-SSPM-EXT: __riscv_sspm 1000000{{$}}
17161716

17171717
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1718-
// RUN: -march=rv32i_supm0p8 -E -dM %s \
1718+
// RUN: -march=rv32i_supm1p0 -E -dM %s \
17191719
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
17201720
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1721-
// RUN: -march=rv64i_supm0p8 -E -dM %s \
1721+
// RUN: -march=rv64i_supm1p0 -E -dM %s \
17221722
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
1723-
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
1723+
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
17241724

17251725
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
17261726
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -263,7 +263,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
263263
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
264264

265265
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
266-
LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`__.
266+
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.
267267

268268
``experimental-ssqosid``
269269
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.

‎llvm/docs/ReleaseNotes.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ Changes to the RISC-V Backend
176176
* The names of the majority of the S-prefixed (supervisor-level) extension
177177
names in the RISC-V profiles specification are now recognised.
178178
* Codegen support was added for the Zimop (May-Be-Operations) extension.
179-
* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
179+
* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 1.0.0 Pointer Masking extensions are supported.
180180
* The experimental Ssqosid extension is supported.
181181
* Zacas is no longer experimental.
182182
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -961,32 +961,32 @@ def FeatureStdExtSvpbmt
961961
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
962962
// present.
963963
def FeatureStdExtSsnpm
964-
: RISCVExperimentalExtension<"ssnpm", 0, 8,
964+
: RISCVExperimentalExtension<"ssnpm", 1, 0,
965965
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
966966

967967
// A machine-level extension that provides pointer masking for the next lower
968968
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
969969
def FeatureStdExtSmnpm
970-
: RISCVExperimentalExtension<"smnpm", 0, 8,
970+
: RISCVExperimentalExtension<"smnpm", 1, 0,
971971
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
972972

973973
// A machine-level extension that provides pointer masking for M-mode.
974974
def FeatureStdExtSmmpm
975-
: RISCVExperimentalExtension<"smmpm", 0, 8,
975+
: RISCVExperimentalExtension<"smmpm", 1, 0,
976976
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
977977

978978
// An extension that indicates that there is pointer-masking support available
979979
// in supervisor mode, with some facility provided in the supervisor execution
980980
// environment to control pointer masking.
981981
def FeatureStdExtSspm
982-
: RISCVExperimentalExtension<"sspm", 0, 8,
982+
: RISCVExperimentalExtension<"sspm", 1, 0,
983983
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
984984

985985
// An extension that indicates that there is pointer-masking support available
986986
// in user mode, with some facility provided in the application execution
987987
// environment to control pointer masking.
988988
def FeatureStdExtSupm
989-
: RISCVExperimentalExtension<"supm", 0, 8,
989+
: RISCVExperimentalExtension<"supm", 1, 0,
990990
"'Supm' (Indicates User-mode Pointer Masking)">;
991991

992992
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -406,11 +406,11 @@
406406
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
407407
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4_zicsr2p0"
408408
; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
409-
; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm0p8"
410-
; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm0p8"
411-
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
412-
; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
413-
; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
409+
; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0"
410+
; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm1p0"
411+
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
412+
; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
413+
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
414414
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
415415

416416
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
@@ -542,11 +542,11 @@
542542
; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
543543
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4_zicsr2p0"
544544
; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0"
545-
; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm0p8"
546-
; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm0p8"
547-
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
548-
; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
549-
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
545+
; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0"
546+
; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm1p0"
547+
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
548+
; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
549+
; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
550550
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
551551

552552
; RVI20U32: .attribute 5, "rv32i2p1"
@@ -556,7 +556,7 @@
556556
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
557557
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
558558
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
559-
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
559+
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
560560
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
561561
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
562562
; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"

‎llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -417,32 +417,32 @@
417417
.attribute arch, "rv64i_xsfvfwmaccqqq"
418418
# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"
419419

420-
.attribute arch, "rv32i_ssnpm0p8"
421-
# CHECK: attribute 5, "rv32i2p1_ssnpm0p8"
420+
.attribute arch, "rv32i_ssnpm1p0"
421+
# CHECK: attribute 5, "rv32i2p1_ssnpm1p0"
422422

423-
.attribute arch, "rv32i_smnpm0p8"
424-
# CHECK: attribute 5, "rv32i2p1_smnpm0p8"
423+
.attribute arch, "rv32i_smnpm1p0"
424+
# CHECK: attribute 5, "rv32i2p1_smnpm1p0"
425425

426-
.attribute arch, "rv32i_smmpm0p8"
427-
# CHECK: attribute 5, "rv32i2p1_smmpm0p8"
426+
.attribute arch, "rv32i_smmpm1p0"
427+
# CHECK: attribute 5, "rv32i2p1_smmpm1p0"
428428

429-
.attribute arch, "rv32i_sspm0p8"
430-
# CHECK: attribute 5, "rv32i2p1_sspm0p8"
429+
.attribute arch, "rv32i_sspm1p0"
430+
# CHECK: attribute 5, "rv32i2p1_sspm1p0"
431431

432-
.attribute arch, "rv32i_supm0p8"
433-
# CHECK: attribute 5, "rv32i2p1_supm0p8"
432+
.attribute arch, "rv32i_supm1p0"
433+
# CHECK: attribute 5, "rv32i2p1_supm1p0"
434434

435-
.attribute arch, "rv64i_ssnpm0p8"
436-
# CHECK: attribute 5, "rv64i2p1_ssnpm0p8"
435+
.attribute arch, "rv64i_ssnpm1p0"
436+
# CHECK: attribute 5, "rv64i2p1_ssnpm1p0"
437437

438-
.attribute arch, "rv64i_smnpm0p8"
439-
# CHECK: attribute 5, "rv64i2p1_smnpm0p8"
438+
.attribute arch, "rv64i_smnpm1p0"
439+
# CHECK: attribute 5, "rv64i2p1_smnpm1p0"
440440

441-
.attribute arch, "rv64i_smmpm0p8"
442-
# CHECK: attribute 5, "rv64i2p1_smmpm0p8"
441+
.attribute arch, "rv64i_smmpm1p0"
442+
# CHECK: attribute 5, "rv64i2p1_smmpm1p0"
443443

444-
.attribute arch, "rv64i_sspm0p8"
445-
# CHECK: attribute 5, "rv64i2p1_sspm0p8"
444+
.attribute arch, "rv64i_sspm1p0"
445+
# CHECK: attribute 5, "rv64i2p1_sspm1p0"
446446

447-
.attribute arch, "rv64i_supm0p8"
448-
# CHECK: attribute 5, "rv64i2p1_supm0p8"
447+
.attribute arch, "rv64i_supm1p0"
448+
# CHECK: attribute 5, "rv64i2p1_supm1p0"

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1077,12 +1077,12 @@ Experimental extensions
10771077
ztso 0.1
10781078
zvfbfmin 1.0
10791079
zvfbfwma 1.0
1080-
smmpm 0.8
1081-
smnpm 0.8
1082-
ssnpm 0.8
1083-
sspm 0.8
1080+
smmpm 1.0
1081+
smnpm 1.0
1082+
ssnpm 1.0
1083+
sspm 1.0
10841084
ssqosid 1.0
1085-
supm 0.8
1085+
supm 1.0
10861086
10871087
Supported Profiles
10881088
rva20s64

0 commit comments

Comments
 (0)