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[X86][MC] Support enc/dec for IMULZU. (#86653)
apx-spec: https://cdrdv2.intel.com/v1/dl/getContent/784266 apx-syntax-recommendation: https://cdrdv2.intel.com/v1/dl/getContent/817241
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‎llvm/lib/Target/X86/X86InstrArithmetic.td

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@@ -334,6 +334,44 @@ let Predicates = [In64BitMode] in {
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def IMUL32rmi_EVEX : IMulOpMI_RF<Xi32, WriteIMul32Imm>, PL;
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def IMUL64rmi32_EVEX : IMulOpMI_RF<Xi64, WriteIMul64Imm>, PL;
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}
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// IMULZU instructions
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class IMulZUOpRI8_R<X86TypeInfo t, X86FoldableSchedWrite sched>
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: BinOpRI8<0x6B, "imulzu", binop_ndd_args, t, MRMSrcReg,
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(outs t.RegClass:$dst)> {
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let SchedRW = [sched];
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}
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class IMulZUOpRI_R<X86TypeInfo t, X86FoldableSchedWrite sched>
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: BinOpRI<0x69, "imulzu", binop_ndd_args, t, MRMSrcReg,
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(outs t.RegClass:$dst), []> {
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let SchedRW = [sched];
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}
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class IMulZUOpMI8_R<X86TypeInfo t, X86FoldableSchedWrite sched>
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: BinOpMI8<"imulzu", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
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let Opcode = 0x6B;
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let SchedRW = [sched.Folded];
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}
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class IMulZUOpMI_R<X86TypeInfo t, X86FoldableSchedWrite sched>
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: BinOpMI<0x69, "imulzu", binop_ndd_args, t, MRMSrcMem,
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(outs t.RegClass:$dst), []> {
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let SchedRW = [sched.Folded];
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}
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let Defs = [EFLAGS], Predicates = [HasEGPR, In64BitMode] in {
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def IMULZU16rri8 : IMulZUOpRI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
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def IMULZU16rmi8 : IMulZUOpMI8_R<Xi16, WriteIMul16Imm>, ZU, PD;
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def IMULZU16rri : IMulZUOpRI_R<Xi16, WriteIMul16Imm>, ZU, PD;
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def IMULZU16rmi : IMulZUOpMI_R<Xi16, WriteIMul16Imm>, ZU, PD;
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def IMULZU32rri8 : IMulZUOpRI8_R<Xi32, WriteIMul32Imm>, ZU;
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def IMULZU32rmi8 : IMulZUOpMI8_R<Xi32, WriteIMul32Imm>, ZU;
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def IMULZU32rri : IMulZUOpRI_R<Xi32, WriteIMul32Imm>, ZU;
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def IMULZU32rmi : IMulZUOpMI_R<Xi32, WriteIMul32Imm>, ZU;
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def IMULZU64rri8 : IMulZUOpRI8_R<Xi64, WriteIMul64Imm>, ZU;
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def IMULZU64rmi8 : IMulZUOpMI8_R<Xi64, WriteIMul64Imm>, ZU;
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def IMULZU64rri32 : IMulZUOpRI_R<Xi64, WriteIMul64Imm>, ZU;
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def IMULZU64rmi32 : IMulZUOpMI_R<Xi64, WriteIMul64Imm>, ZU;
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}
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//===----------------------------------------------------------------------===//
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// INC and DEC Instructions
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//

‎llvm/lib/Target/X86/X86InstrUtils.td

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@@ -119,6 +119,8 @@ class NDD<bit ndd> {
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class NF: T_MAP4, EVEX, EVEX_NF;
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// PL - Helper for promoted legacy instructions
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class PL: T_MAP4, EVEX, ExplicitEVEXPrefix;
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// ZU - Helper for Zero Upper instructions
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class ZU: T_MAP4, EVEX, EVEX_B;
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//===----------------------------------------------------------------------===//
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// X86 Type infomation definitions

‎llvm/test/MC/Disassembler/X86/apx/imulzu.txt

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# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
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# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
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# ATT: imulzuw $123, %dx, %dx
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# INTEL: imulzu dx, dx, 123
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0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b
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# ATT: imulzul $123, %ecx, %ecx
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# INTEL: imulzu ecx, ecx, 123
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0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b
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# ATT: imulzuq $123, %r9, %r9
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# INTEL: imulzu r9, r9, 123
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0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b
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# ATT: imulzuw $123, 291(%r8,%rax,4), %dx
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# INTEL: imulzu dx, word ptr [r8 + 4*rax + 291], 123
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0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b
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# ATT: imulzul $123, 291(%r8,%rax,4), %ecx
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# INTEL: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
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0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b
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# ATT: imulzuq $123, 291(%r8,%rax,4), %r9
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# INTEL: imulzu r9, qword ptr [r8 + 4*rax + 291], 123
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0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b
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# ATT: imulzuw $1234, %dx, %dx
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# INTEL: imulzu dx, dx, 1234
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0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04
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# ATT: imulzuw $1234, 291(%r8,%rax,4), %dx
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# INTEL: imulzu dx, word ptr [r8 + 4*rax + 291], 1234
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0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04
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# ATT: imulzul $123456, %ecx, %ecx
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# INTEL: imulzu ecx, ecx, 123456
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0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00
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# ATT: imulzuq $123456, %r9, %r9
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# INTEL: imulzu r9, r9, 123456
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0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00
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# ATT: imulzul $123456, 291(%r8,%rax,4), %ecx
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# INTEL: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
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0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00
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# ATT: imulzuq $123456, 291(%r8,%rax,4), %r9
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# INTEL: imulzu r9, qword ptr [r8 + 4*rax + 291], 123456
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0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00

‎llvm/test/MC/X86/apx/imulzu-att.s

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# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
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# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
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# ERROR-COUNT-12: error:
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# ERROR-NOT: error:
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# CHECK: imulzuw $123, %dx, %dx
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# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b]
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imulzuw $123, %dx, %dx
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# CHECK: imulzul $123, %ecx, %ecx
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# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b]
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imulzul $123, %ecx, %ecx
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# CHECK: imulzuq $123, %r9, %r9
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b]
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imulzuq $123, %r9, %r9
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# CHECK: imulzuw $123, 291(%r8,%rax,4), %dx
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# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzuw $123, 291(%r8,%rax,4), %dx
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# CHECK: imulzul $123, 291(%r8,%rax,4), %ecx
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# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzul $123, 291(%r8,%rax,4), %ecx
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# CHECK: imulzuq $123, 291(%r8,%rax,4), %r9
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzuq $123, 291(%r8,%rax,4), %r9
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# CHECK: imulzuw $1234, %dx, %dx
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# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04]
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imulzuw $1234, %dx, %dx
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# CHECK: imulzuw $1234, 291(%r8,%rax,4), %dx
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# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04]
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imulzuw $1234, 291(%r8,%rax,4), %dx
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# CHECK: imulzul $123456, %ecx, %ecx
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# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
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imulzul $123456, %ecx, %ecx
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# CHECK: imulzuq $123456, %r9, %r9
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
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imulzuq $123456, %r9, %r9
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# CHECK: imulzul $123456, 291(%r8,%rax,4), %ecx
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# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
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imulzul $123456, 291(%r8,%rax,4), %ecx
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# CHECK: imulzuq $123456, 291(%r8,%rax,4), %r9
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
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imulzuq $123456, 291(%r8,%rax,4), %r9

‎llvm/test/MC/X86/apx/imulzu-intel.s

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# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
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# CHECK: imulzu dx, dx, 123
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# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x6b,0xd2,0x7b]
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imulzu dx, dx, 123
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# CHECK: imulzu ecx, ecx, 123
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# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x6b,0xc9,0x7b]
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imulzu ecx, ecx, 123
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# CHECK: imulzu r9, r9, 123
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0xc9,0x7b]
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imulzu r9, r9, 123
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# CHECK: imulzu dx, word ptr [r8 + 4*rax + 291], 123
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# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x6b,0x94,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzu dx, word ptr [r8 + 4*rax + 291], 123
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# CHECK: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
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# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzu ecx, dword ptr [r8 + 4*rax + 291], 123
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# CHECK: imulzu r9, qword ptr [r8 + 4*rax + 291], 123
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x6b,0x8c,0x80,0x23,0x01,0x00,0x00,0x7b]
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imulzu r9, qword ptr [r8 + 4*rax + 291], 123
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# CHECK: imulzu dx, dx, 1234
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# CHECK: encoding: [0x62,0xf4,0x7d,0x18,0x69,0xd2,0xd2,0x04]
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imulzu dx, dx, 1234
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# CHECK: imulzu dx, word ptr [r8 + 4*rax + 291], 1234
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# CHECK: encoding: [0x62,0xd4,0x7d,0x18,0x69,0x94,0x80,0x23,0x01,0x00,0x00,0xd2,0x04]
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imulzu dx, word ptr [r8 + 4*rax + 291], 1234
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# CHECK: imulzu ecx, ecx, 123456
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# CHECK: encoding: [0x62,0xf4,0x7c,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
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imulzu ecx, ecx, 123456
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# CHECK: imulzu r9, r9, 123456
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0xc9,0x40,0xe2,0x01,0x00]
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imulzu r9, r9, 123456
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# CHECK: imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
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# CHECK: encoding: [0x62,0xd4,0x7c,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
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imulzu ecx, dword ptr [r8 + 4*rax + 291], 123456
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# CHECK: imulzu r9, qword ptr [r8 + 4*rax + 291], 123456
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# CHECK: encoding: [0x62,0x54,0xfc,0x18,0x69,0x8c,0x80,0x23,0x01,0x00,0x00,0x40,0xe2,0x01,0x00]
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imulzu r9, qword ptr [r8 + 4*rax + 291], 123456

‎llvm/test/TableGen/x86-fold-tables.inc

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@@ -756,6 +756,12 @@ static const X86FoldTableEntry Table1[] = {
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{X86::IMUL64rri32_NF, X86::IMUL64rmi32_NF, 0},
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{X86::IMUL64rri8, X86::IMUL64rmi8, 0},
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{X86::IMUL64rri8_NF, X86::IMUL64rmi8_NF, 0},
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{X86::IMULZU16rri, X86::IMULZU16rmi, 0},
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{X86::IMULZU16rri8, X86::IMULZU16rmi8, 0},
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{X86::IMULZU32rri, X86::IMULZU32rmi, 0},
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{X86::IMULZU32rri8, X86::IMULZU32rmi8, 0},
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{X86::IMULZU64rri32, X86::IMULZU64rmi32, 0},
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{X86::IMULZU64rri8, X86::IMULZU64rmi8, 0},
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{X86::INC16r_ND, X86::INC16m_ND, 0},
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{X86::INC16r_NF_ND, X86::INC16m_NF_ND, 0},
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{X86::INC32r_ND, X86::INC32m_ND, 0},

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