Review feedback

Author: jurahul

llvm/utils/TableGen/FastISelEmitter.cpp

@@ -158,8 +158,9 @@ struct OperandsSignature {
   OperandsSignature getWithoutImmCodes() const {
     OperandsSignature Result;
     Result.Operands.resize(Operands.size());
-    for (auto [RO, O] : zip_equal(Result.Operands, Operands))
-      RO = O.isImm() ? OpKind::getImm(0) : O;
+    llvm::transform(Operands, Result.Operands.begin(), [](OpKind Kind) {
+      return Kind.isImm() ? OpKind::getImm(0) : Kind;
+    });
     return Result;
   }
 
@@ -311,7 +312,7 @@ struct OperandsSignature {
   void PrintArguments(raw_ostream &OS, ArrayRef<std::string> PhyRegs) const {
     ListSeparator LS;
     for (const auto [Idx, Opnd, PhyReg] : enumerate(Operands, PhyRegs)) {
-      if (PhyReg != "") {
+      if (!PhyReg.empty()) {
         // Implicit physical register operand.
         continue;
       }
@@ -346,8 +347,8 @@ struct OperandsSignature {
   void PrintManglingSuffix(raw_ostream &OS, ArrayRef<std::string> PhyRegs,
                            ImmPredicateSet &ImmPredicates,
                            bool StripImmCodes = false) const {
-    for (const auto [PR, Opnd] : zip_equal(PhyRegs, Operands)) {
-      if (PR != "") {
+    for (const auto [PhyReg, Opnd] : zip_equal(PhyRegs, Operands)) {
+      if (!PhyReg.empty()) {
         // Implicit physical register operand. e.g. Instruction::Mul expect to
         // select to a binary op. On x86, mul may take a single operand with
         // the other operand being implicit. We must emit something that looks
@@ -361,7 +362,7 @@ struct OperandsSignature {
 
   void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
                            bool StripImmCodes = false) const {
-    for (const OpKind Opnd : Operands)
+    for (OpKind Opnd : Operands)
       Opnd.printManglingSuffix(OS, ImmPredicates, StripImmCodes);
   }
 };
@@ -638,7 +639,7 @@ void FastISelMap::emitInstructionCode(raw_ostream &OS,
     }
 
     for (const auto [Idx, PhyReg] : enumerate(Memo.PhysRegs)) {
-      if (PhyReg != "")
+      if (!PhyReg.empty())
         OS << "  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, "
            << "TII.get(TargetOpcode::COPY), " << PhyReg << ").addReg(Op" << Idx
            << ");\n";