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[RISCV] Allow folding vmerge with implicit merge operand when true has tied dest
We currently don't fold a vmerge if it has an implicit merge operand and its true operand has a tied dest (i.e. has a passthru operand). This restriction was added in https://reviews.llvm.org/D151596, back whenever we had separate TU/TA pseudos. It looks like it was added because the policy might not have been handled correctly. However the policy should be set correctly if we relax this restriction today, since we compute the policy differently now that we have removed the TU/TA distinction in our pseudos. We use a TUMU policy, and relax it to TAMU iff the vmerge's merge operand is implicit. The reasoning behind this being that the tail elements always come from the vmerge's merge operand[1], so if the merge operand is implicit-def then the tail is implicit-def, and hence tail agnostic. [1] unless the VL was shrunk, in which case we conservatively use TUMU.
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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3645,11 +3645,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
36453645
// If True has a merge operand then it needs to be the same as vmerge's False,
36463646
// since False will be used for the result's merge operand.
36473647
if (HasTiedDest && !isImplicitDef(True->getOperand(0))) {
3648-
// The vmerge instruction must be TU.
3649-
// FIXME: This could be relaxed, but we need to handle the policy for the
3650-
// resulting op correctly.
3651-
if (isImplicitDef(Merge))
3652-
return false;
36533648
SDValue MergeOpTrue = True->getOperand(0);
36543649
if (False != MergeOpTrue)
36553650
return false;
@@ -3659,9 +3654,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
36593654
// going to keep the mask from True.
36603655
if (IsMasked) {
36613656
assert(HasTiedDest && "Expected tied dest");
3662-
// The vmerge instruction must be TU.
3663-
if (isImplicitDef(Merge))
3664-
return false;
36653657
// FIXME: Support mask agnostic True instruction which would have an
36663658
// undef merge operand.
36673659
if (Mask && !usesAllOnesMask(Mask, Glue))

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Lines changed: 4 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1203,17 +1203,11 @@ define <vscale x 2 x i64> @vpmerge_vwsub.w_tied(<vscale x 2 x i64> %passthru, <v
12031203
%b = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> %mask, <vscale x 2 x i64> %a, <vscale x 2 x i64> %passthru, i32 %vl)
12041204
ret <vscale x 2 x i64> %b
12051205

1206-
; FIXME: We don't currently handle vmerge with an implicit passthru if the true
1207-
; operand also has a tied dest. This could be folded into a masked vmacc with ta
1208-
; policy.
12091206
define <vscale x 2 x i32> @true_tied_dest_vmerge_implicit_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl) {
12101207
; CHECK-LABEL: true_tied_dest_vmerge_implicit_passthru:
12111208
; CHECK: # %bb.0:
1212-
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
1213-
; CHECK-NEXT: vmv1r.v v11, v8
1214-
; CHECK-NEXT: vmacc.vv v11, v9, v10
1215-
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1216-
; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0
1209+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
1210+
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
12171211
; CHECK-NEXT: ret
12181212
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %avl, i64 0)
12191213
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
@@ -1226,16 +1220,11 @@ define <vscale x 2 x i32> @true_tied_dest_vmerge_implicit_passthru(<vscale x 2 x
12261220
ret <vscale x 2 x i32> %b
12271221
}
12281222

1229-
; FIXME: We don't currently handle vmerge with an implicit passthru if the true
1230-
; operand also has a tied dest, e.g. has a passthru since it's a masked
1231-
; pseudo. This could be folded into a masked vadd with ta policy.
12321223
define <vscale x 2 x i32> @true_mask_vmerge_implicit_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl) {
12331224
; CHECK-LABEL: true_mask_vmerge_implicit_passthru:
12341225
; CHECK: # %bb.0:
1235-
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
1236-
; CHECK-NEXT: vmv1r.v v11, v8
1237-
; CHECK-NEXT: vadd.vv v11, v9, v10, v0.t
1238-
; CHECK-NEXT: vmv.v.v v8, v11
1226+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
1227+
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
12391228
; CHECK-NEXT: ret
12401229
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl, i64 0)
12411230
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(

‎llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll

Lines changed: 44 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -91,9 +91,8 @@ define <vscale x 1 x i8> @vmadd_vv_nxv1i8_ta(<vscale x 1 x i8> %a, <vscale x 1 x
9191
define <vscale x 1 x i8> @vmadd_vx_nxv1i8_ta(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
9292
; CHECK-LABEL: vmadd_vx_nxv1i8_ta:
9393
; CHECK: # %bb.0:
94-
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
95-
; CHECK-NEXT: vmacc.vx v9, a0, v8
96-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
94+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
95+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
9796
; CHECK-NEXT: ret
9897
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
9998
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -192,9 +191,8 @@ define <vscale x 2 x i8> @vmadd_vv_nxv2i8_ta(<vscale x 2 x i8> %a, <vscale x 2 x
192191
define <vscale x 2 x i8> @vmadd_vx_nxv2i8_ta(<vscale x 2 x i8> %a, i8 %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
193192
; CHECK-LABEL: vmadd_vx_nxv2i8_ta:
194193
; CHECK: # %bb.0:
195-
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
196-
; CHECK-NEXT: vmacc.vx v9, a0, v8
197-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
194+
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
195+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
198196
; CHECK-NEXT: ret
199197
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
200198
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -293,9 +291,8 @@ define <vscale x 4 x i8> @vmadd_vv_nxv4i8_ta(<vscale x 4 x i8> %a, <vscale x 4 x
293291
define <vscale x 4 x i8> @vmadd_vx_nxv4i8_ta(<vscale x 4 x i8> %a, i8 %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
294292
; CHECK-LABEL: vmadd_vx_nxv4i8_ta:
295293
; CHECK: # %bb.0:
296-
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
297-
; CHECK-NEXT: vmacc.vx v9, a0, v8
298-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
294+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
295+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
299296
; CHECK-NEXT: ret
300297
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
301298
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -394,9 +391,8 @@ define <vscale x 8 x i8> @vmadd_vv_nxv8i8_ta(<vscale x 8 x i8> %a, <vscale x 8 x
394391
define <vscale x 8 x i8> @vmadd_vx_nxv8i8_ta(<vscale x 8 x i8> %a, i8 %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
395392
; CHECK-LABEL: vmadd_vx_nxv8i8_ta:
396393
; CHECK: # %bb.0:
397-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
398-
; CHECK-NEXT: vmacc.vx v9, a0, v8
399-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
394+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
395+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
400396
; CHECK-NEXT: ret
401397
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
402398
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -495,9 +491,8 @@ define <vscale x 16 x i8> @vmadd_vv_nxv16i8_ta(<vscale x 16 x i8> %a, <vscale x
495491
define <vscale x 16 x i8> @vmadd_vx_nxv16i8_ta(<vscale x 16 x i8> %a, i8 %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
496492
; CHECK-LABEL: vmadd_vx_nxv16i8_ta:
497493
; CHECK: # %bb.0:
498-
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
499-
; CHECK-NEXT: vmacc.vx v10, a0, v8
500-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
494+
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
495+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
501496
; CHECK-NEXT: ret
502497
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
503498
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -596,9 +591,8 @@ define <vscale x 32 x i8> @vmadd_vv_nxv32i8_ta(<vscale x 32 x i8> %a, <vscale x
596591
define <vscale x 32 x i8> @vmadd_vx_nxv32i8_ta(<vscale x 32 x i8> %a, i8 %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
597592
; CHECK-LABEL: vmadd_vx_nxv32i8_ta:
598593
; CHECK: # %bb.0:
599-
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
600-
; CHECK-NEXT: vmacc.vx v12, a0, v8
601-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
594+
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
595+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
602596
; CHECK-NEXT: ret
603597
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
604598
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -700,9 +694,8 @@ define <vscale x 64 x i8> @vmadd_vv_nxv64i8_ta(<vscale x 64 x i8> %a, <vscale x
700694
define <vscale x 64 x i8> @vmadd_vx_nxv64i8_ta(<vscale x 64 x i8> %a, i8 %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {
701695
; CHECK-LABEL: vmadd_vx_nxv64i8_ta:
702696
; CHECK: # %bb.0:
703-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
704-
; CHECK-NEXT: vmacc.vx v16, a0, v8
705-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
697+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
698+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
706699
; CHECK-NEXT: ret
707700
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
708701
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -801,9 +794,8 @@ define <vscale x 1 x i16> @vmadd_vv_nxv1i16_ta(<vscale x 1 x i16> %a, <vscale x
801794
define <vscale x 1 x i16> @vmadd_vx_nxv1i16_ta(<vscale x 1 x i16> %a, i16 %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
802795
; CHECK-LABEL: vmadd_vx_nxv1i16_ta:
803796
; CHECK: # %bb.0:
804-
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
805-
; CHECK-NEXT: vmacc.vx v9, a0, v8
806-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
797+
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
798+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
807799
; CHECK-NEXT: ret
808800
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
809801
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -902,9 +894,8 @@ define <vscale x 2 x i16> @vmadd_vv_nxv2i16_ta(<vscale x 2 x i16> %a, <vscale x
902894
define <vscale x 2 x i16> @vmadd_vx_nxv2i16_ta(<vscale x 2 x i16> %a, i16 %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
903895
; CHECK-LABEL: vmadd_vx_nxv2i16_ta:
904896
; CHECK: # %bb.0:
905-
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
906-
; CHECK-NEXT: vmacc.vx v9, a0, v8
907-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
897+
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
898+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
908899
; CHECK-NEXT: ret
909900
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
910901
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -1003,9 +994,8 @@ define <vscale x 4 x i16> @vmadd_vv_nxv4i16_ta(<vscale x 4 x i16> %a, <vscale x
1003994
define <vscale x 4 x i16> @vmadd_vx_nxv4i16_ta(<vscale x 4 x i16> %a, i16 %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1004995
; CHECK-LABEL: vmadd_vx_nxv4i16_ta:
1005996
; CHECK: # %bb.0:
1006-
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
1007-
; CHECK-NEXT: vmacc.vx v9, a0, v8
1008-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
997+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
998+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
1009999
; CHECK-NEXT: ret
10101000
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
10111001
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -1104,9 +1094,8 @@ define <vscale x 8 x i16> @vmadd_vv_nxv8i16_ta(<vscale x 8 x i16> %a, <vscale x
11041094
define <vscale x 8 x i16> @vmadd_vx_nxv8i16_ta(<vscale x 8 x i16> %a, i16 %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
11051095
; CHECK-LABEL: vmadd_vx_nxv8i16_ta:
11061096
; CHECK: # %bb.0:
1107-
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
1108-
; CHECK-NEXT: vmacc.vx v10, a0, v8
1109-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
1097+
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
1098+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
11101099
; CHECK-NEXT: ret
11111100
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
11121101
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1205,9 +1194,8 @@ define <vscale x 16 x i16> @vmadd_vv_nxv16i16_ta(<vscale x 16 x i16> %a, <vscale
12051194
define <vscale x 16 x i16> @vmadd_vx_nxv16i16_ta(<vscale x 16 x i16> %a, i16 %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
12061195
; CHECK-LABEL: vmadd_vx_nxv16i16_ta:
12071196
; CHECK: # %bb.0:
1208-
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
1209-
; CHECK-NEXT: vmacc.vx v12, a0, v8
1210-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
1197+
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
1198+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
12111199
; CHECK-NEXT: ret
12121200
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
12131201
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -1309,9 +1297,8 @@ define <vscale x 32 x i16> @vmadd_vv_nxv32i16_ta(<vscale x 32 x i16> %a, <vscale
13091297
define <vscale x 32 x i16> @vmadd_vx_nxv32i16_ta(<vscale x 32 x i16> %a, i16 %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
13101298
; CHECK-LABEL: vmadd_vx_nxv32i16_ta:
13111299
; CHECK: # %bb.0:
1312-
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
1313-
; CHECK-NEXT: vmacc.vx v16, a0, v8
1314-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
1300+
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
1301+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
13151302
; CHECK-NEXT: ret
13161303
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
13171304
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -1410,9 +1397,8 @@ define <vscale x 1 x i32> @vmadd_vv_nxv1i32_ta(<vscale x 1 x i32> %a, <vscale x
14101397
define <vscale x 1 x i32> @vmadd_vx_nxv1i32_ta(<vscale x 1 x i32> %a, i32 %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
14111398
; CHECK-LABEL: vmadd_vx_nxv1i32_ta:
14121399
; CHECK: # %bb.0:
1413-
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1414-
; CHECK-NEXT: vmacc.vx v9, a0, v8
1415-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
1400+
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
1401+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
14161402
; CHECK-NEXT: ret
14171403
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
14181404
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1511,9 +1497,8 @@ define <vscale x 2 x i32> @vmadd_vv_nxv2i32_ta(<vscale x 2 x i32> %a, <vscale x
15111497
define <vscale x 2 x i32> @vmadd_vx_nxv2i32_ta(<vscale x 2 x i32> %a, i32 %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
15121498
; CHECK-LABEL: vmadd_vx_nxv2i32_ta:
15131499
; CHECK: # %bb.0:
1514-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
1515-
; CHECK-NEXT: vmacc.vx v9, a0, v8
1516-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
1500+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
1501+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
15171502
; CHECK-NEXT: ret
15181503
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
15191504
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1612,9 +1597,8 @@ define <vscale x 4 x i32> @vmadd_vv_nxv4i32_ta(<vscale x 4 x i32> %a, <vscale x
16121597
define <vscale x 4 x i32> @vmadd_vx_nxv4i32_ta(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
16131598
; CHECK-LABEL: vmadd_vx_nxv4i32_ta:
16141599
; CHECK: # %bb.0:
1615-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
1616-
; CHECK-NEXT: vmacc.vx v10, a0, v8
1617-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
1600+
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
1601+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
16181602
; CHECK-NEXT: ret
16191603
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
16201604
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1713,9 +1697,8 @@ define <vscale x 8 x i32> @vmadd_vv_nxv8i32_ta(<vscale x 8 x i32> %a, <vscale x
17131697
define <vscale x 8 x i32> @vmadd_vx_nxv8i32_ta(<vscale x 8 x i32> %a, i32 %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
17141698
; CHECK-LABEL: vmadd_vx_nxv8i32_ta:
17151699
; CHECK: # %bb.0:
1716-
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
1717-
; CHECK-NEXT: vmacc.vx v12, a0, v8
1718-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
1700+
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
1701+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
17191702
; CHECK-NEXT: ret
17201703
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
17211704
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1817,9 +1800,8 @@ define <vscale x 16 x i32> @vmadd_vv_nxv16i32_ta(<vscale x 16 x i32> %a, <vscale
18171800
define <vscale x 16 x i32> @vmadd_vx_nxv16i32_ta(<vscale x 16 x i32> %a, i32 %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
18181801
; CHECK-LABEL: vmadd_vx_nxv16i32_ta:
18191802
; CHECK: # %bb.0:
1820-
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
1821-
; CHECK-NEXT: vmacc.vx v16, a0, v8
1822-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
1803+
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
1804+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
18231805
; CHECK-NEXT: ret
18241806
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
18251807
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1965,9 +1947,8 @@ define <vscale x 1 x i64> @vmadd_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, <v
19651947
;
19661948
; RV64-LABEL: vmadd_vx_nxv1i64_ta:
19671949
; RV64: # %bb.0:
1968-
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1969-
; RV64-NEXT: vmacc.vx v9, a0, v8
1970-
; RV64-NEXT: vmerge.vvm v8, v8, v9, v0
1950+
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
1951+
; RV64-NEXT: vmadd.vx v8, a0, v9, v0.t
19711952
; RV64-NEXT: ret
19721953
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
19731954
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -2113,9 +2094,8 @@ define <vscale x 2 x i64> @vmadd_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, <v
21132094
;
21142095
; RV64-LABEL: vmadd_vx_nxv2i64_ta:
21152096
; RV64: # %bb.0:
2116-
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
2117-
; RV64-NEXT: vmacc.vx v10, a0, v8
2118-
; RV64-NEXT: vmerge.vvm v8, v8, v10, v0
2097+
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
2098+
; RV64-NEXT: vmadd.vx v8, a0, v10, v0.t
21192099
; RV64-NEXT: ret
21202100
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
21212101
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -2261,9 +2241,8 @@ define <vscale x 4 x i64> @vmadd_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, <v
22612241
;
22622242
; RV64-LABEL: vmadd_vx_nxv4i64_ta:
22632243
; RV64: # %bb.0:
2264-
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
2265-
; RV64-NEXT: vmacc.vx v12, a0, v8
2266-
; RV64-NEXT: vmerge.vvm v8, v8, v12, v0
2244+
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
2245+
; RV64-NEXT: vmadd.vx v8, a0, v12, v0.t
22672246
; RV64-NEXT: ret
22682247
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
22692248
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -2412,9 +2391,8 @@ define <vscale x 8 x i64> @vmadd_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, <v
24122391
;
24132392
; RV64-LABEL: vmadd_vx_nxv8i64_ta:
24142393
; RV64: # %bb.0:
2415-
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
2416-
; RV64-NEXT: vmacc.vx v16, a0, v8
2417-
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
2394+
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
2395+
; RV64-NEXT: vmadd.vx v8, a0, v16, v0.t
24182396
; RV64-NEXT: ret
24192397
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
24202398
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

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