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[RISCV] Add isel patterns for generating Xqcibi branch instructions (#139872)
Add ISEL patterns for generating the Xqcibi branch immediate instructions. Similar to #135771 adds new CondCodes for the various branch instructions and uses them to return the appropriate instruction.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2401,6 +2401,8 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
24012401

24022402
if (auto *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
24032403
int64_t C = RHSC->getSExtValue();
2404+
const RISCVSubtarget &Subtarget =
2405+
DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
24042406
switch (CC) {
24052407
default: break;
24062408
case ISD::SETGT:
@@ -2410,6 +2412,13 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
24102412
CC = ISD::SETGE;
24112413
return;
24122414
}
2415+
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1)) {
2416+
// We have a branch immediate instruction for SETGE but not SETGT.
2417+
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
2418+
RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
2419+
CC = ISD::SETGE;
2420+
return;
2421+
}
24132422
break;
24142423
case ISD::SETLT:
24152424
// Convert X < 1 to 0 >= X.
@@ -2420,6 +2429,16 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
24202429
return;
24212430
}
24222431
break;
2432+
case ISD::SETUGT:
2433+
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1) &&
2434+
C != -1) {
2435+
// We have a branch immediate instruction for SETUGE but not SETUGT.
2436+
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
2437+
RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
2438+
CC = ISD::SETUGE;
2439+
return;
2440+
}
2441+
break;
24232442
}
24242443
}
24252444

@@ -21331,6 +21350,10 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2133121350
return emitReadCounterWidePseudo(MI, BB);
2133221351
case RISCV::Select_GPR_Using_CC_GPR:
2133321352
case RISCV::Select_GPR_Using_CC_Imm:
21353+
case RISCV::Select_GPR_Using_CC_Simm5NonZero:
21354+
case RISCV::Select_GPR_Using_CC_Uimm5NonZero:
21355+
case RISCV::Select_GPR_Using_CC_Simm16NonZero:
21356+
case RISCV::Select_GPR_Using_CC_Uimm16NonZero:
2133421357
case RISCV::Select_FPR16_Using_CC_GPR:
2133521358
case RISCV::Select_FPR16INX_Using_CC_GPR:
2133621359
case RISCV::Select_FPR32_Using_CC_GPR:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -977,6 +977,30 @@ static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
977977
return RISCVCC::COND_CV_BEQIMM;
978978
case RISCV::CV_BNEIMM:
979979
return RISCVCC::COND_CV_BNEIMM;
980+
case RISCV::QC_BEQI:
981+
return RISCVCC::COND_QC_BEQI;
982+
case RISCV::QC_E_BEQI:
983+
return RISCVCC::COND_QC_E_BEQI;
984+
case RISCV::QC_BNEI:
985+
return RISCVCC::COND_QC_BNEI;
986+
case RISCV::QC_E_BNEI:
987+
return RISCVCC::COND_QC_E_BNEI;
988+
case RISCV::QC_BLTI:
989+
return RISCVCC::COND_QC_BLTI;
990+
case RISCV::QC_E_BLTI:
991+
return RISCVCC::COND_QC_E_BLTI;
992+
case RISCV::QC_BGEI:
993+
return RISCVCC::COND_QC_BGEI;
994+
case RISCV::QC_E_BGEI:
995+
return RISCVCC::COND_QC_E_BGEI;
996+
case RISCV::QC_BLTUI:
997+
return RISCVCC::COND_QC_BLTUI;
998+
case RISCV::QC_E_BLTUI:
999+
return RISCVCC::COND_QC_E_BLTUI;
1000+
case RISCV::QC_BGEUI:
1001+
return RISCVCC::COND_QC_BGEUI;
1002+
case RISCV::QC_E_BGEUI:
1003+
return RISCVCC::COND_QC_E_BGEUI;
9801004
}
9811005
}
9821006

@@ -1034,6 +1058,30 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
10341058
return RISCV::CV_BEQIMM;
10351059
case RISCVCC::COND_CV_BNEIMM:
10361060
return RISCV::CV_BNEIMM;
1061+
case RISCVCC::COND_QC_BEQI:
1062+
return RISCV::QC_BEQI;
1063+
case RISCVCC::COND_QC_E_BEQI:
1064+
return RISCV::QC_E_BEQI;
1065+
case RISCVCC::COND_QC_BNEI:
1066+
return RISCV::QC_BNEI;
1067+
case RISCVCC::COND_QC_E_BNEI:
1068+
return RISCV::QC_E_BNEI;
1069+
case RISCVCC::COND_QC_BLTI:
1070+
return RISCV::QC_BLTI;
1071+
case RISCVCC::COND_QC_E_BLTI:
1072+
return RISCV::QC_E_BLTI;
1073+
case RISCVCC::COND_QC_BGEI:
1074+
return RISCV::QC_BGEI;
1075+
case RISCVCC::COND_QC_E_BGEI:
1076+
return RISCV::QC_E_BGEI;
1077+
case RISCVCC::COND_QC_BLTUI:
1078+
return RISCV::QC_BLTUI;
1079+
case RISCVCC::COND_QC_E_BLTUI:
1080+
return RISCV::QC_E_BLTUI;
1081+
case RISCVCC::COND_QC_BGEUI:
1082+
return RISCV::QC_BGEUI;
1083+
case RISCVCC::COND_QC_E_BGEUI:
1084+
return RISCV::QC_E_BGEUI;
10371085
}
10381086
}
10391087

@@ -1061,6 +1109,30 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
10611109
return RISCVCC::COND_CV_BNEIMM;
10621110
case RISCVCC::COND_CV_BNEIMM:
10631111
return RISCVCC::COND_CV_BEQIMM;
1112+
case RISCVCC::COND_QC_BEQI:
1113+
return RISCVCC::COND_QC_BNEI;
1114+
case RISCVCC::COND_QC_E_BEQI:
1115+
return RISCVCC::COND_QC_E_BNEI;
1116+
case RISCVCC::COND_QC_BNEI:
1117+
return RISCVCC::COND_QC_BEQI;
1118+
case RISCVCC::COND_QC_E_BNEI:
1119+
return RISCVCC::COND_QC_E_BEQI;
1120+
case RISCVCC::COND_QC_BLTI:
1121+
return RISCVCC::COND_QC_BGEI;
1122+
case RISCVCC::COND_QC_E_BLTI:
1123+
return RISCVCC::COND_QC_E_BGEI;
1124+
case RISCVCC::COND_QC_BGEI:
1125+
return RISCVCC::COND_QC_BLTI;
1126+
case RISCVCC::COND_QC_E_BGEI:
1127+
return RISCVCC::COND_QC_E_BLTI;
1128+
case RISCVCC::COND_QC_BLTUI:
1129+
return RISCVCC::COND_QC_BGEUI;
1130+
case RISCVCC::COND_QC_E_BLTUI:
1131+
return RISCVCC::COND_QC_E_BGEUI;
1132+
case RISCVCC::COND_QC_BGEUI:
1133+
return RISCVCC::COND_QC_BLTUI;
1134+
case RISCVCC::COND_QC_E_BGEUI:
1135+
return RISCVCC::COND_QC_E_BLTUI;
10641136
}
10651137
}
10661138

@@ -1436,6 +1508,18 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
14361508
case RISCV::BGEU:
14371509
case RISCV::CV_BEQIMM:
14381510
case RISCV::CV_BNEIMM:
1511+
case RISCV::QC_BEQI:
1512+
case RISCV::QC_BNEI:
1513+
case RISCV::QC_BGEI:
1514+
case RISCV::QC_BLTI:
1515+
case RISCV::QC_BLTUI:
1516+
case RISCV::QC_BGEUI:
1517+
case RISCV::QC_E_BEQI:
1518+
case RISCV::QC_E_BNEI:
1519+
case RISCV::QC_E_BGEI:
1520+
case RISCV::QC_E_BLTI:
1521+
case RISCV::QC_E_BLTUI:
1522+
case RISCV::QC_E_BGEUI:
14391523
return isIntN(13, BrOffset);
14401524
case RISCV::JAL:
14411525
case RISCV::PseudoBR:
@@ -2617,6 +2701,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
26172701
case RISCVOp::OPERAND_UIMM5_LSB0:
26182702
Ok = isShiftedUInt<4, 1>(Imm);
26192703
break;
2704+
case RISCVOp::OPERAND_UIMM5_NONZERO:
2705+
Ok = isUInt<5>(Imm) && (Imm != 0);
2706+
break;
26202707
case RISCVOp::OPERAND_UIMM6_LSB0:
26212708
Ok = isShiftedUInt<5, 1>(Imm);
26222709
break;
@@ -2644,6 +2731,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
26442731
case RISCVOp::OPERAND_UIMM10_LSB00_NONZERO:
26452732
Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0);
26462733
break;
2734+
case RISCVOp::OPERAND_UIMM16_NONZERO:
2735+
Ok = isUInt<16>(Imm) && (Imm != 0);
2736+
break;
26472737
case RISCVOp::OPERAND_ZERO:
26482738
Ok = Imm == 0;
26492739
break;
@@ -2663,6 +2753,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
26632753
case RISCVOp::OPERAND_SIMM5_PLUS1:
26642754
Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
26652755
break;
2756+
case RISCVOp::OPERAND_SIMM5_NONZERO:
2757+
Ok = isInt<5>(Imm) && (Imm != 0);
2758+
break;
26662759
case RISCVOp::OPERAND_SIMM6_NONZERO:
26672760
Ok = Imm != 0 && isInt<6>(Imm);
26682761
break;
@@ -2675,6 +2768,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
26752768
case RISCVOp::OPERAND_SIMM12_LSB00000:
26762769
Ok = isShiftedInt<7, 5>(Imm);
26772770
break;
2771+
case RISCVOp::OPERAND_SIMM16_NONZERO:
2772+
Ok = isInt<16>(Imm) && (Imm != 0);
2773+
break;
26782774
case RISCVOp::OPERAND_SIMM20_LI:
26792775
Ok = isInt<20>(Imm);
26802776
break;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,18 @@ enum CondCode {
4343
COND_GEU,
4444
COND_CV_BEQIMM,
4545
COND_CV_BNEIMM,
46+
COND_QC_BEQI,
47+
COND_QC_BNEI,
48+
COND_QC_BLTI,
49+
COND_QC_BGEI,
50+
COND_QC_BLTUI,
51+
COND_QC_BGEUI,
52+
COND_QC_E_BEQI,
53+
COND_QC_E_BNEI,
54+
COND_QC_E_BLTI,
55+
COND_QC_E_BGEI,
56+
COND_QC_E_BLTUI,
57+
COND_QC_E_BGEUI,
4658
COND_INVALID
4759
};
4860

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 92 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,36 @@ def AddLike: PatFrags<(ops node:$A, node:$B),
188188
def AddShl : PatFrag<(ops node:$Ra, node:$Rb, node:$SH3),
189189
(add node:$Ra, (shl node:$Rb, node:$SH3))>;
190190

191+
def IntCCtoQCRISCVCC : SDNodeXForm<riscv_selectcc, [{
192+
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
193+
int64_t Imm = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
194+
RISCVCC::CondCode BrCC;
195+
switch (CC) {
196+
default:
197+
report_fatal_error("Unexpected CondCode for Xqcibi branch instructions");
198+
case ISD::SETEQ:
199+
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BEQI : RISCVCC::COND_QC_E_BEQI;
200+
break;
201+
case ISD::SETNE:
202+
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BNEI : RISCVCC::COND_QC_E_BNEI;
203+
break;
204+
case ISD::SETLT:
205+
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BLTI : RISCVCC::COND_QC_E_BLTI;
206+
break;
207+
case ISD::SETGE:
208+
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BGEI : RISCVCC::COND_QC_E_BGEI;
209+
break;
210+
case ISD::SETULT:
211+
BrCC = isUInt<5>(Imm) ? RISCVCC::COND_QC_BLTUI : RISCVCC::COND_QC_E_BLTUI;
212+
break;
213+
case ISD::SETUGE:
214+
BrCC = isUInt<5>(Imm) ? RISCVCC::COND_QC_BGEUI : RISCVCC::COND_QC_E_BGEUI;
215+
break;
216+
}
217+
return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
218+
}]>;
219+
220+
191221
//===----------------------------------------------------------------------===//
192222
// Instruction Formats
193223
//===----------------------------------------------------------------------===//
@@ -1288,6 +1318,36 @@ class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
12881318
: Pat<(StoreOp (i32 GPR:$rd), (AddShl (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
12891319
(Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;
12901320

1321+
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
1322+
class BcciPat<CondCode Cond, QCIBranchInst_rii Inst, DAGOperand InTyImm>
1323+
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
1324+
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
1325+
1326+
class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
1327+
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
1328+
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
1329+
1330+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, usesCustomInserter = 1 in {
1331+
def Select_GPR_Using_CC_Simm5NonZero : Pseudo<(outs GPR:$dst),
1332+
(ins GPR:$lhs, simm5nonzero:$imm5,
1333+
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1334+
def Select_GPR_Using_CC_Uimm5NonZero : Pseudo<(outs GPR:$dst),
1335+
(ins GPR:$lhs, uimm5nonzero:$imm5,
1336+
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1337+
def Select_GPR_Using_CC_Simm16NonZero : Pseudo<(outs GPR:$dst),
1338+
(ins GPR:$lhs, simm16nonzero:$imm16,
1339+
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1340+
def Select_GPR_Using_CC_Uimm16NonZero : Pseudo<(outs GPR:$dst),
1341+
(ins GPR:$lhs, uimm16nonzero:$imm16,
1342+
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1343+
}
1344+
1345+
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
1346+
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
1347+
(i32 GPR:$truev), GPR:$falsev),
1348+
(OpNode GPR:$lhs, InTyImm:$Constant,
1349+
(IntCCtoQCRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
1350+
12911351
/// Simple arithmetic operations
12921352

12931353
let Predicates = [HasVendorXqcilia, IsRV32] in {
@@ -1342,6 +1402,38 @@ def : PatGprNoX0GprNoX0<ushlsat, QC_SHLUSAT>;
13421402
def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
13431403
} // Predicates = [HasVendorXqcia, IsRV32]
13441404

1405+
/// Branches
1406+
1407+
let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 in {
1408+
def : BcciPat<SETEQ, QC_BEQI, simm5nonzero>;
1409+
def : BcciPat<SETNE, QC_BNEI, simm5nonzero>;
1410+
def : BcciPat<SETLT, QC_BLTI, simm5nonzero>;
1411+
def : BcciPat<SETGE, QC_BGEI, simm5nonzero>;
1412+
def : BcciPat<SETULT, QC_BLTUI, uimm5nonzero>;
1413+
def : BcciPat<SETUGE, QC_BGEUI, uimm5nonzero>;
1414+
1415+
def : Bcci48Pat<SETEQ, QC_E_BEQI, simm16nonzero>;
1416+
def : Bcci48Pat<SETNE, QC_E_BNEI, simm16nonzero>;
1417+
def : Bcci48Pat<SETLT, QC_E_BLTI, simm16nonzero>;
1418+
def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
1419+
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
1420+
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
1421+
1422+
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1423+
def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1424+
def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1425+
def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1426+
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;
1427+
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;
1428+
1429+
def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1430+
def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1431+
def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1432+
def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1433+
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
1434+
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
1435+
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
1436+
13451437
let Predicates = [HasVendorXqciint, IsRV32] in
13461438
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
13471439

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