Skip to content

Commit dc91961

Browse files
s-barannikovs-barannikov
committed
Hexagon
1 parent ac63fd8 commit dc91961

File tree

5 files changed

+119
-157
lines changed

5 files changed

+119
-157
lines changed

‎llvm/lib/Target/Hexagon/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ tablegen(LLVM HexagonGenDisassemblerTables.inc -gen-disassembler)
1111
tablegen(LLVM HexagonGenInstrInfo.inc -gen-instr-info)
1212
tablegen(LLVM HexagonGenMCCodeEmitter.inc -gen-emitter)
1313
tablegen(LLVM HexagonGenRegisterInfo.inc -gen-register-info)
14+
tablegen(LLVM HexagonGenSDNodeInfo.inc -gen-sd-node-info)
1415
tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget)
1516

1617
add_public_tablegen_target(HexagonCommonTableGen)

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1892,64 +1892,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
18921892
setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
18931893
}
18941894

1895-
const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1896-
switch ((HexagonISD::NodeType)Opcode) {
1897-
case HexagonISD::ADDC: return "HexagonISD::ADDC";
1898-
case HexagonISD::SUBC: return "HexagonISD::SUBC";
1899-
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1900-
case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1901-
case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1902-
case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1903-
case HexagonISD::CALL: return "HexagonISD::CALL";
1904-
case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1905-
case HexagonISD::CALLR: return "HexagonISD::CALLR";
1906-
case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1907-
case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1908-
case HexagonISD::CONST32: return "HexagonISD::CONST32";
1909-
case HexagonISD::CP: return "HexagonISD::CP";
1910-
case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1911-
case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1912-
case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1913-
case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1914-
case HexagonISD::INSERT: return "HexagonISD::INSERT";
1915-
case HexagonISD::JT: return "HexagonISD::JT";
1916-
case HexagonISD::RET_GLUE: return "HexagonISD::RET_GLUE";
1917-
case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1918-
case HexagonISD::VASL: return "HexagonISD::VASL";
1919-
case HexagonISD::VASR: return "HexagonISD::VASR";
1920-
case HexagonISD::VLSR: return "HexagonISD::VLSR";
1921-
case HexagonISD::MFSHL: return "HexagonISD::MFSHL";
1922-
case HexagonISD::MFSHR: return "HexagonISD::MFSHR";
1923-
case HexagonISD::SSAT: return "HexagonISD::SSAT";
1924-
case HexagonISD::USAT: return "HexagonISD::USAT";
1925-
case HexagonISD::SMUL_LOHI: return "HexagonISD::SMUL_LOHI";
1926-
case HexagonISD::UMUL_LOHI: return "HexagonISD::UMUL_LOHI";
1927-
case HexagonISD::USMUL_LOHI: return "HexagonISD::USMUL_LOHI";
1928-
case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1929-
case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1930-
case HexagonISD::VROR: return "HexagonISD::VROR";
1931-
case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1932-
case HexagonISD::READTIMER: return "HexagonISD::READTIMER";
1933-
case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1934-
case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1935-
case HexagonISD::D2P: return "HexagonISD::D2P";
1936-
case HexagonISD::P2D: return "HexagonISD::P2D";
1937-
case HexagonISD::V2Q: return "HexagonISD::V2Q";
1938-
case HexagonISD::Q2V: return "HexagonISD::Q2V";
1939-
case HexagonISD::QCAT: return "HexagonISD::QCAT";
1940-
case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1941-
case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1942-
case HexagonISD::TL_EXTEND: return "HexagonISD::TL_EXTEND";
1943-
case HexagonISD::TL_TRUNCATE: return "HexagonISD::TL_TRUNCATE";
1944-
case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1945-
case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1946-
case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1947-
case HexagonISD::ISEL: return "HexagonISD::ISEL";
1948-
case HexagonISD::OP_END: break;
1949-
}
1950-
return nullptr;
1951-
}
1952-
19531895
bool
19541896
HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign,
19551897
const SDLoc &dl, SelectionDAG &DAG) const {
@@ -3343,8 +3285,6 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
33433285
default:
33443286
#ifndef NDEBUG
33453287
Op.getNode()->dumpr(&DAG);
3346-
if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
3347-
errs() << "Error: check for a non-legal type in this operation\n";
33483288
#endif
33493289
llvm_unreachable("Should not custom lower this!");
33503290

‎llvm/lib/Target/Hexagon/HexagonISelLowering.h

Lines changed: 0 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -29,99 +29,6 @@
2929

3030
namespace llvm {
3131

32-
namespace HexagonISD {
33-
34-
enum NodeType : unsigned {
35-
OP_BEGIN = ISD::BUILTIN_OP_END,
36-
37-
CONST32 = OP_BEGIN,
38-
CONST32_GP, // For marking data present in GP.
39-
ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
40-
SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
41-
ALLOCA,
42-
43-
AT_GOT, // Index in GOT.
44-
AT_PCREL, // Offset relative to PC.
45-
46-
CALL, // Function call.
47-
CALLnr, // Function call that does not return.
48-
CALLR,
49-
50-
RET_GLUE, // Return with a glue operand.
51-
BARRIER, // Memory barrier.
52-
JT, // Jump table.
53-
CP, // Constant pool.
54-
55-
COMBINE,
56-
VASL, // Vector shifts by a scalar value
57-
VASR,
58-
VLSR,
59-
MFSHL, // Funnel shifts with the shift amount guaranteed to be
60-
MFSHR, // within the range of the bit width of the element.
61-
62-
SSAT, // Signed saturate.
63-
USAT, // Unsigned saturate.
64-
SMUL_LOHI, // Same as ISD::SMUL_LOHI, but opaque to the combiner.
65-
UMUL_LOHI, // Same as ISD::UMUL_LOHI, but opaque to the combiner.
66-
// We want to legalize MULH[SU] to [SU]MUL_LOHI, but the
67-
// combiner will keep rewriting it back to MULH[SU].
68-
USMUL_LOHI, // Like SMUL_LOHI, but unsigned*signed.
69-
70-
TSTBIT,
71-
INSERT,
72-
EXTRACTU,
73-
VEXTRACTW,
74-
VINSERTW0,
75-
VROR,
76-
TC_RETURN,
77-
EH_RETURN,
78-
DCFETCH,
79-
READCYCLE,
80-
READTIMER,
81-
PTRUE,
82-
PFALSE,
83-
D2P, // Convert 8-byte value to 8-bit predicate register. [*]
84-
P2D, // Convert 8-bit predicate register to 8-byte value. [*]
85-
V2Q, // Convert HVX vector to a vector predicate reg. [*]
86-
Q2V, // Convert vector predicate to an HVX vector. [*]
87-
// [*] The equivalence is defined as "Q <=> (V != 0)",
88-
// where the != operation compares bytes.
89-
// Note: V != 0 is implemented as V >u 0.
90-
QCAT,
91-
QTRUE,
92-
QFALSE,
93-
94-
TL_EXTEND, // Wrappers for ISD::*_EXTEND and ISD::TRUNCATE to prevent DAG
95-
TL_TRUNCATE, // from auto-folding operations, e.g.
96-
// (i32 ext (i16 ext i8)) would be folded to (i32 ext i8).
97-
// To simplify the type legalization, we want to keep these
98-
// single steps separate during type legalization.
99-
// TL_[EXTEND|TRUNCATE] Inp, i128 _, i32 Opc
100-
// * Inp is the original input to extend/truncate,
101-
// * _ is a dummy operand with an illegal type (can be undef),
102-
// * Opc is the original opcode.
103-
// The legalization process (in Hexagon lowering code) will
104-
// first deal with the "real" types (i.e. Inp and the result),
105-
// and once all of them are processed, the wrapper node will
106-
// be replaced with the original ISD node. The dummy illegal
107-
// operand is there to make sure that the legalization hooks
108-
// are called again after everything else is legal, giving
109-
// us the opportunity to undo the wrapping.
110-
111-
TYPECAST, // No-op that's used to convert between different legal
112-
// types in a register.
113-
VALIGN, // Align two vectors (in Op0, Op1) to one that would have
114-
// been loaded from address in Op2.
115-
VALIGNADDR, // Align vector address: Op0 & -Op1, except when it is
116-
// an address in a vector load, then it's a no-op.
117-
ISEL, // Marker for nodes that were created during ISel, and
118-
// which need explicit selection (would have been left
119-
// unselected otherwise).
120-
OP_END
121-
};
122-
123-
} // end namespace HexagonISD
124-
12532
class HexagonSubtarget;
12633

12734
class HexagonTargetLowering : public TargetLowering {
@@ -182,8 +89,6 @@ class HexagonTargetLowering : public TargetLowering {
18289
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
18390
SelectionDAG &DAG) const override;
18491

185-
const char *getTargetNodeName(unsigned Opcode) const override;
186-
18792
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
18893
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
18994
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;

‎llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,71 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13+
#include "HexagonSelectionDAGInfo.h"
1314
#include "HexagonTargetMachine.h"
1415
#include "llvm/CodeGen/SelectionDAG.h"
16+
17+
#define GET_SDNODE_DESC
18+
#include "HexagonGenSDNodeInfo.inc"
19+
1520
using namespace llvm;
1621

1722
#define DEBUG_TYPE "hexagon-selectiondag-info"
1823

24+
HexagonSelectionDAGInfo::HexagonSelectionDAGInfo()
25+
: SelectionDAGGenTargetInfo(HexagonGenSDNodeInfo) {}
26+
27+
const char *HexagonSelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
28+
// These nodes don't have corresponding entries in *.td files yet.
29+
switch (static_cast<HexagonISD::NodeType>(Opcode)) {
30+
case HexagonISD::ADDC:
31+
return "HexagonISD::ADDC";
32+
case HexagonISD::SUBC:
33+
return "HexagonISD::SUBC";
34+
case HexagonISD::CALLR:
35+
return "HexagonISD::CALLR";
36+
case HexagonISD::SMUL_LOHI:
37+
return "HexagonISD::SMUL_LOHI";
38+
case HexagonISD::UMUL_LOHI:
39+
return "HexagonISD::UMUL_LOHI";
40+
case HexagonISD::USMUL_LOHI:
41+
return "HexagonISD::USMUL_LOHI";
42+
case HexagonISD::VROR:
43+
return "HexagonISD::VROR";
44+
case HexagonISD::D2P:
45+
return "HexagonISD::D2P";
46+
case HexagonISD::P2D:
47+
return "HexagonISD::P2D";
48+
case HexagonISD::V2Q:
49+
return "HexagonISD::V2Q";
50+
case HexagonISD::Q2V:
51+
return "HexagonISD::Q2V";
52+
case HexagonISD::TL_EXTEND:
53+
return "HexagonISD::TL_EXTEND";
54+
case HexagonISD::TL_TRUNCATE:
55+
return "HexagonISD::TL_TRUNCATE";
56+
case HexagonISD::TYPECAST:
57+
return "HexagonISD::TYPECAST";
58+
case HexagonISD::ISEL:
59+
return "HexagonISD::ISEL";
60+
}
61+
62+
return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
63+
}
64+
65+
void HexagonSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
66+
const SDNode *N) const {
67+
switch (N->getOpcode()) {
68+
default:
69+
break;
70+
case HexagonISD::VALIGNADDR:
71+
// invalid number of operands; expected 1, got 2
72+
return;
73+
}
74+
75+
SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
76+
}
77+
1978
SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy(
2079
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
2180
SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,

‎llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h

Lines changed: 59 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,68 @@
1515

1616
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
1717

18+
#define GET_SDNODE_ENUM
19+
#include "HexagonGenSDNodeInfo.inc"
20+
1821
namespace llvm {
22+
namespace HexagonISD {
23+
24+
enum NodeType : unsigned {
25+
ADDC = GENERATED_OPCODE_END, // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
26+
SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
27+
28+
CALLR,
29+
30+
SMUL_LOHI, // Same as ISD::SMUL_LOHI, but opaque to the combiner.
31+
UMUL_LOHI, // Same as ISD::UMUL_LOHI, but opaque to the combiner.
32+
// We want to legalize MULH[SU] to [SU]MUL_LOHI, but the
33+
// combiner will keep rewriting it back to MULH[SU].
34+
USMUL_LOHI, // Like SMUL_LOHI, but unsigned*signed.
35+
36+
VROR,
37+
D2P, // Convert 8-byte value to 8-bit predicate register. [*]
38+
P2D, // Convert 8-bit predicate register to 8-byte value. [*]
39+
V2Q, // Convert HVX vector to a vector predicate reg. [*]
40+
Q2V, // Convert vector predicate to an HVX vector. [*]
41+
// [*] The equivalence is defined as "Q <=> (V != 0)",
42+
// where the != operation compares bytes.
43+
// Note: V != 0 is implemented as V >u 0.
44+
45+
TL_EXTEND, // Wrappers for ISD::*_EXTEND and ISD::TRUNCATE to prevent DAG
46+
TL_TRUNCATE, // from auto-folding operations, e.g.
47+
// (i32 ext (i16 ext i8)) would be folded to (i32 ext i8).
48+
// To simplify the type legalization, we want to keep these
49+
// single steps separate during type legalization.
50+
// TL_[EXTEND|TRUNCATE] Inp, i128 _, i32 Opc
51+
// * Inp is the original input to extend/truncate,
52+
// * _ is a dummy operand with an illegal type (can be undef),
53+
// * Opc is the original opcode.
54+
// The legalization process (in Hexagon lowering code) will
55+
// first deal with the "real" types (i.e. Inp and the result),
56+
// and once all of them are processed, the wrapper node will
57+
// be replaced with the original ISD node. The dummy illegal
58+
// operand is there to make sure that the legalization hooks
59+
// are called again after everything else is legal, giving
60+
// us the opportunity to undo the wrapping.
1961

20-
class HexagonSelectionDAGInfo : public SelectionDAGTargetInfo {
62+
TYPECAST, // No-op that's used to convert between different legal
63+
// types in a register.
64+
ISEL, // Marker for nodes that were created during ISel, and
65+
// which need explicit selection (would have been left
66+
// unselected otherwise).
67+
// clang-format on
68+
};
69+
70+
} // namespace HexagonISD
71+
72+
class HexagonSelectionDAGInfo : public SelectionDAGGenTargetInfo {
2173
public:
22-
explicit HexagonSelectionDAGInfo() = default;
74+
HexagonSelectionDAGInfo();
75+
76+
const char *getTargetNodeName(unsigned Opcode) const override;
77+
78+
void verifyTargetNode(const SelectionDAG &DAG,
79+
const SDNode *N) const override;
2380

2481
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
2582
SDValue Chain, SDValue Dst, SDValue Src,

0 commit comments

Comments
 (0)