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[LoopVectorize] Propagate fast-math flags for inloop reductions
This patch updates VPReductionRecipe::execute so that the fast-math flags associated with the underlying instruction of the VPRecipe are propagated through to the reductions which are created. Differential Revision: https://reviews.llvm.org/D112548
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+140
-22
lines changed

4 files changed

+140
-22
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9776,6 +9776,9 @@ void VPReductionRecipe::execute(VPTransformState &State) {
97769776
Value *PrevInChain = State.get(getChainOp(), 0);
97779777
RecurKind Kind = RdxDesc->getRecurrenceKind();
97789778
bool IsOrdered = State.ILV->useOrderedReductions(*RdxDesc);
9779+
// Propagate the fast-math flags carried by the underlying instruction.
9780+
IRBuilderBase::FastMathFlagGuard FMFGuard(State.Builder);
9781+
State.Builder.setFastMathFlags(RdxDesc->getFastMathFlags());
97799782
for (unsigned Part = 0; Part < State.UF; ++Part) {
97809783
Value *NewVecOp = State.get(getVecOp(), Part);
97819784
if (VPValue *Cond = getCondOp()) {

‎llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,52 @@ for.end:
4949
ret float %add
5050
}
5151

52+
; Same as above but where fadd has a fast-math flag.
53+
define float @fadd_strict_fmf(float* noalias nocapture readonly %a, i64 %n) {
54+
; CHECK-ORDERED-LABEL: @fadd_strict_fmf
55+
; CHECK-ORDERED: vector.body:
56+
; CHECK-ORDERED: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %vector.ph ], [ [[RDX:%.*]], %vector.body ]
57+
; CHECK-ORDERED: [[LOAD_VEC:%.*]] = load <8 x float>, <8 x float>*
58+
; CHECK-ORDERED: [[RDX]] = call nnan float @llvm.vector.reduce.fadd.v8f32(float [[VEC_PHI]], <8 x float> [[LOAD_VEC]])
59+
; CHECK-ORDERED: for.end:
60+
; CHECK-ORDERED: [[RES:%.*]] = phi float [ [[SCALAR:%.*]], %for.body ], [ [[RDX]], %middle.block ]
61+
; CHECK-ORDERED: ret float [[RES]]
62+
63+
; CHECK-UNORDERED-LABEL: @fadd_strict_fmf
64+
; CHECK-UNORDERED: vector.body:
65+
; CHECK-UNORDERED: [[VEC_PHI:%.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %vector.ph ], [ [[FADD_VEC:%.*]], %vector.body ]
66+
; CHECK-UNORDERED: [[LOAD_VEC:%.*]] = load <8 x float>, <8 x float>*
67+
; CHECK-UNORDERED: [[FADD_VEC]] = fadd nnan <8 x float> [[LOAD_VEC]], [[VEC_PHI]]
68+
; CHECK-UNORDERED-NOT: @llvm.vector.reduce.fadd
69+
; CHECK-UNORDERED: middle.block:
70+
; CHECK-UNORDERED: [[RDX:%.*]] = call nnan float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> [[FADD_VEC]])
71+
; CHECK-UNORDERED: for.body:
72+
; CHECK-UNORDERED: [[LOAD:%.*]] = load float, float*
73+
; CHECK-UNORDERED: [[FADD:%.*]] = fadd nnan float [[LOAD]], {{.*}}
74+
; CHECK-UNORDERED: for.end:
75+
; CHECK-UNORDERED: [[RES:%.*]] = phi float [ [[FADD]], %for.body ], [ [[RDX]], %middle.block ]
76+
; CHECK-UNORDERED: ret float [[RES]]
77+
78+
; CHECK-NOT-VECTORIZED-LABEL: @fadd_strict_fmf
79+
; CHECK-NOT-VECTORIZED-NOT: vector.body
80+
81+
entry:
82+
br label %for.body
83+
84+
for.body:
85+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
86+
%sum.07 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
87+
%arrayidx = getelementptr inbounds float, float* %a, i64 %iv
88+
%0 = load float, float* %arrayidx, align 4
89+
%add = fadd nnan float %0, %sum.07
90+
%iv.next = add nuw nsw i64 %iv, 1
91+
%exitcond.not = icmp eq i64 %iv.next, %n
92+
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !0
93+
94+
for.end:
95+
ret float %add
96+
}
97+
5298
define float @fadd_strict_unroll(float* noalias nocapture readonly %a, i64 %n) {
5399
; CHECK-ORDERED-LABEL: @fadd_strict_unroll
54100
; CHECK-ORDERED: vector.body:
@@ -767,6 +813,79 @@ for.end:
767813
ret float %add
768814
}
769815

816+
; Same as above but where fadd has a fast-math flag.
817+
define float @fadd_scalar_vf_fmf(float* noalias nocapture readonly %a, i64 %n) {
818+
; CHECK-ORDERED-LABEL: @fadd_scalar_vf_fmf
819+
; CHECK-ORDERED: vector.body:
820+
; CHECK-ORDERED: [[VEC_PHI:%.*]] = phi float [ 0.000000e+00, %vector.ph ], [ [[FADD4:%.*]], %vector.body ]
821+
; CHECK-ORDERED: [[LOAD1:%.*]] = load float, float*
822+
; CHECK-ORDERED: [[LOAD2:%.*]] = load float, float*
823+
; CHECK-ORDERED: [[LOAD3:%.*]] = load float, float*
824+
; CHECK-ORDERED: [[LOAD4:%.*]] = load float, float*
825+
; CHECK-ORDERED: [[FADD1:%.*]] = fadd nnan float [[VEC_PHI]], [[LOAD1]]
826+
; CHECK-ORDERED: [[FADD2:%.*]] = fadd nnan float [[FADD1]], [[LOAD2]]
827+
; CHECK-ORDERED: [[FADD3:%.*]] = fadd nnan float [[FADD2]], [[LOAD3]]
828+
; CHECK-ORDERED: [[FADD4]] = fadd nnan float [[FADD3]], [[LOAD4]]
829+
; CHECK-ORDERED-NOT: @llvm.vector.reduce.fadd
830+
; CHECK-ORDERED: scalar.ph:
831+
; CHECK-ORDERED: [[MERGE_RDX:%.*]] = phi float [ 0.000000e+00, %entry ], [ [[FADD4]], %middle.block ]
832+
; CHECK-ORDERED: for.body:
833+
; CHECK-ORDERED: [[SUM_07:%.*]] = phi float [ [[MERGE_RDX]], %scalar.ph ], [ [[FADD5:%.*]], %for.body ]
834+
; CHECK-ORDERED: [[LOAD5:%.*]] = load float, float*
835+
; CHECK-ORDERED: [[FADD5]] = fadd nnan float [[LOAD5]], [[SUM_07]]
836+
; CHECK-ORDERED: for.end:
837+
; CHECK-ORDERED: [[RES:%.*]] = phi float [ [[FADD5]], %for.body ], [ [[FADD4]], %middle.block ]
838+
; CHECK-ORDERED: ret float [[RES]]
839+
840+
; CHECK-UNORDERED-LABEL: @fadd_scalar_vf_fmf
841+
; CHECK-UNORDERED: vector.body:
842+
; CHECK-UNORDERED: [[VEC_PHI1:%.*]] = phi float [ 0.000000e+00, %vector.ph ], [ [[FADD1:%.*]], %vector.body ]
843+
; CHECK-UNORDERED: [[VEC_PHI2:%.*]] = phi float [ -0.000000e+00, %vector.ph ], [ [[FADD2:%.*]], %vector.body ]
844+
; CHECK-UNORDERED: [[VEC_PHI3:%.*]] = phi float [ -0.000000e+00, %vector.ph ], [ [[FADD3:%.*]], %vector.body ]
845+
; CHECK-UNORDERED: [[VEC_PHI4:%.*]] = phi float [ -0.000000e+00, %vector.ph ], [ [[FADD4:%.*]], %vector.body ]
846+
; CHECK-UNORDERED: [[LOAD1:%.*]] = load float, float*
847+
; CHECK-UNORDERED: [[LOAD2:%.*]] = load float, float*
848+
; CHECK-UNORDERED: [[LOAD3:%.*]] = load float, float*
849+
; CHECK-UNORDERED: [[LOAD4:%.*]] = load float, float*
850+
; CHECK-UNORDERED: [[FADD1]] = fadd nnan float [[LOAD1]], [[VEC_PHI1]]
851+
; CHECK-UNORDERED: [[FADD2]] = fadd nnan float [[LOAD2]], [[VEC_PHI2]]
852+
; CHECK-UNORDERED: [[FADD3]] = fadd nnan float [[LOAD3]], [[VEC_PHI3]]
853+
; CHECK-UNORDERED: [[FADD4]] = fadd nnan float [[LOAD4]], [[VEC_PHI4]]
854+
; CHECK-UNORDERED-NOT: @llvm.vector.reduce.fadd
855+
; CHECK-UNORDERED: middle.block:
856+
; CHECK-UNORDERED: [[BIN_RDX1:%.*]] = fadd nnan float [[FADD2]], [[FADD1]]
857+
; CHECK-UNORDERED: [[BIN_RDX2:%.*]] = fadd nnan float [[FADD3]], [[BIN_RDX1]]
858+
; CHECK-UNORDERED: [[BIN_RDX3:%.*]] = fadd nnan float [[FADD4]], [[BIN_RDX2]]
859+
; CHECK-UNORDERED: scalar.ph:
860+
; CHECK-UNORDERED: [[MERGE_RDX:%.*]] = phi float [ 0.000000e+00, %entry ], [ [[BIN_RDX3]], %middle.block ]
861+
; CHECK-UNORDERED: for.body:
862+
; CHECK-UNORDERED: [[SUM_07:%.*]] = phi float [ [[MERGE_RDX]], %scalar.ph ], [ [[FADD5:%.*]], %for.body ]
863+
; CHECK-UNORDERED: [[LOAD5:%.*]] = load float, float*
864+
; CHECK-UNORDERED: [[FADD5]] = fadd nnan float [[LOAD5]], [[SUM_07]]
865+
; CHECK-UORDERED: for.end
866+
; CHECK-UNORDERED: [[RES:%.*]] = phi float [ [[FADD5]], %for.body ], [ [[BIN_RDX3]], %middle.block ]
867+
; CHECK-UNORDERED: ret float [[RES]]
868+
869+
; CHECK-NOT-VECTORIZED-LABEL: @fadd_scalar_vf_fmf
870+
; CHECK-NOT-VECTORIZED-NOT: vector.body
871+
872+
entry:
873+
br label %for.body
874+
875+
for.body:
876+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
877+
%sum.07 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
878+
%arrayidx = getelementptr inbounds float, float* %a, i64 %iv
879+
%0 = load float, float* %arrayidx, align 4
880+
%add = fadd nnan float %0, %sum.07
881+
%iv.next = add nuw nsw i64 %iv, 1
882+
%exitcond.not = icmp eq i64 %iv.next, %n
883+
br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !4
884+
885+
for.end:
886+
ret float %add
887+
}
888+
770889
; Test case where the reduction step is a first-order recurrence.
771890
define double @reduction_increment_by_first_order_recurrence() {
772891
; CHECK-ORDERED-LABEL: @reduction_increment_by_first_order_recurrence(

‎llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1016,24 +1016,22 @@ define float @reduction_fadd(float* nocapture %A, float* nocapture %B) {
10161016
; CHECK: pred.load.continue6:
10171017
; CHECK-NEXT: [[TMP38:%.*]] = phi <4 x float> [ [[TMP28]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP34]], [[PRED_LOAD_IF5]] ]
10181018
; CHECK-NEXT: [[TMP39:%.*]] = phi <4 x float> [ [[TMP29]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP37]], [[PRED_LOAD_IF5]] ]
1019-
; CHECK-NEXT: [[TMP40:%.*]] = select <4 x i1> [[TMP0]], <4 x float> [[TMP38]], <4 x float> zeroinitializer
1020-
; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP40]])
1021-
; CHECK-NEXT: [[TMP42:%.*]] = fadd float [[TMP41]], [[VEC_PHI]]
1022-
; CHECK-NEXT: [[TMP43:%.*]] = select <4 x i1> [[TMP0]], <4 x float> [[TMP39]], <4 x float> zeroinitializer
1023-
; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[TMP43]])
1024-
; CHECK-NEXT: [[TMP45]] = fadd float [[TMP44]], [[TMP42]]
1019+
; CHECK-NEXT: [[TMP40:%.*]] = select fast <4 x i1> [[TMP0]], <4 x float> [[TMP38]], <4 x float> zeroinitializer
1020+
; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[VEC_PHI]], <4 x float> [[TMP40]])
1021+
; CHECK-NEXT: [[TMP42:%.*]] = select fast <4 x i1> [[TMP0]], <4 x float> [[TMP39]], <4 x float> zeroinitializer
1022+
; CHECK-NEXT: [[TMP43:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[TMP41]], <4 x float> [[TMP42]])
10251023
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
10261024
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
1027-
; CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260
1028-
; CHECK-NEXT: br i1 [[TMP46]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
1025+
; CHECK-NEXT: [[TMP44:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260
1026+
; CHECK-NEXT: br i1 [[TMP44]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
10291027
; CHECK: middle.block:
10301028
; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
10311029
; CHECK: scalar.ph:
10321030
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
10331031
; CHECK: for.body:
10341032
; CHECK-NEXT: br i1 undef, label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP21:![0-9]+]]
10351033
; CHECK: for.end:
1036-
; CHECK-NEXT: [[RESULT_0_LCSSA:%.*]] = phi float [ undef, [[FOR_BODY]] ], [ [[TMP45]], [[MIDDLE_BLOCK]] ]
1034+
; CHECK-NEXT: [[RESULT_0_LCSSA:%.*]] = phi float [ undef, [[FOR_BODY]] ], [ [[TMP43]], [[MIDDLE_BLOCK]] ]
10371035
; CHECK-NEXT: ret float [[RESULT_0_LCSSA]]
10381036
;
10391037
entry:
@@ -1124,12 +1122,12 @@ define float @reduction_fmul(float* nocapture %A, float* nocapture %B) {
11241122
; CHECK: pred.load.continue6:
11251123
; CHECK-NEXT: [[TMP38:%.*]] = phi <4 x float> [ [[TMP28]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP34]], [[PRED_LOAD_IF5]] ]
11261124
; CHECK-NEXT: [[TMP39:%.*]] = phi <4 x float> [ [[TMP29]], [[PRED_LOAD_CONTINUE4]] ], [ [[TMP37]], [[PRED_LOAD_IF5]] ]
1127-
; CHECK-NEXT: [[TMP40:%.*]] = select <4 x i1> [[TMP0]], <4 x float> [[TMP38]], <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
1125+
; CHECK-NEXT: [[TMP40:%.*]] = select fast <4 x i1> [[TMP0]], <4 x float> [[TMP38]], <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
11281126
; CHECK-NEXT: [[TMP41:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[TMP40]])
1129-
; CHECK-NEXT: [[TMP42:%.*]] = fmul float [[TMP41]], [[VEC_PHI]]
1130-
; CHECK-NEXT: [[TMP43:%.*]] = select <4 x i1> [[TMP0]], <4 x float> [[TMP39]], <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
1127+
; CHECK-NEXT: [[TMP42:%.*]] = fmul fast float [[TMP41]], [[VEC_PHI]]
1128+
; CHECK-NEXT: [[TMP43:%.*]] = select fast <4 x i1> [[TMP0]], <4 x float> [[TMP39]], <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
11311129
; CHECK-NEXT: [[TMP44:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[TMP43]])
1132-
; CHECK-NEXT: [[TMP45]] = fmul float [[TMP44]], [[TMP42]]
1130+
; CHECK-NEXT: [[TMP45]] = fmul fast float [[TMP44]], [[TMP42]]
11331131
; CHECK-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4
11341132
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
11351133
; CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[INDEX_NEXT]], 260

‎llvm/test/Transforms/LoopVectorize/reduction-inloop.ll

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -558,21 +558,19 @@ define float @reduction_fadd(float* nocapture %A, float* nocapture %B) {
558558
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 [[INDEX]]
559559
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[TMP2]] to <4 x float>*
560560
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
561-
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[WIDE_LOAD]])
562-
; CHECK-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], [[VEC_PHI]]
563-
; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float -0.000000e+00, <4 x float> [[WIDE_LOAD1]])
564-
; CHECK-NEXT: [[TMP7]] = fadd float [[TMP6]], [[TMP5]]
561+
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
562+
; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.vector.reduce.fadd.v4f32(float [[TMP4]], <4 x float> [[WIDE_LOAD1]])
565563
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
566-
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
567-
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
564+
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
565+
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]]
568566
; CHECK: middle.block:
569567
; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
570568
; CHECK: scalar.ph:
571569
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
572570
; CHECK: for.body:
573571
; CHECK-NEXT: br i1 undef, label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]]
574572
; CHECK: for.end:
575-
; CHECK-NEXT: [[RESULT_0_LCSSA:%.*]] = phi float [ undef, [[FOR_BODY]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ]
573+
; CHECK-NEXT: [[RESULT_0_LCSSA:%.*]] = phi float [ undef, [[FOR_BODY]] ], [ [[TMP5]], [[MIDDLE_BLOCK]] ]
576574
; CHECK-NEXT: ret float [[RESULT_0_LCSSA]]
577575
;
578576
entry:
@@ -613,9 +611,9 @@ define float @reduction_fmul(float* nocapture %A, float* nocapture %B) {
613611
; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[TMP2]] to <4 x float>*
614612
; CHECK-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, <4 x float>* [[TMP3]], align 4
615613
; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD]])
616-
; CHECK-NEXT: [[TMP5:%.*]] = fmul float [[TMP4]], [[VEC_PHI]]
614+
; CHECK-NEXT: [[TMP5:%.*]] = fmul fast float [[TMP4]], [[VEC_PHI]]
617615
; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.vector.reduce.fmul.v4f32(float 1.000000e+00, <4 x float> [[WIDE_LOAD1]])
618-
; CHECK-NEXT: [[TMP7]] = fmul float [[TMP6]], [[TMP5]]
616+
; CHECK-NEXT: [[TMP7]] = fmul fast float [[TMP6]], [[TMP5]]
619617
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
620618
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
621619
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]]

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