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[RISCV] Add Zicond run lines to select-const.ll. NFC
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‎llvm/test/CodeGen/RISCV/select-const.ll

Lines changed: 156 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,14 @@
33
; RUN: | FileCheck -check-prefixes=RV32,RV32I %s
44
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
55
; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
6+
; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \
7+
; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s
68
; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
79
; RUN: | FileCheck -check-prefixes=RV64,RV64I %s
810
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
911
; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s
12+
; RUN: llc -mtriple=riscv64 -mattr=+zicond -target-abi=lp64 -verify-machineinstrs < %s \
13+
; RUN: | FileCheck -check-prefixes=RV64,RV64ZICOND %s
1014

1115
;; This tests how good we are at materialising constants using `select`. The aim
1216
;; is that we do so without a branch if possible (at the moment our lowering of
@@ -59,25 +63,59 @@ define signext i32 @select_const_int_pow2_zero(i1 zeroext %a) nounwind {
5963
}
6064

6165
define signext i32 @select_const_int_harder(i1 zeroext %a) nounwind {
62-
; RV32-LABEL: select_const_int_harder:
63-
; RV32: # %bb.0:
64-
; RV32-NEXT: bnez a0, .LBB3_2
65-
; RV32-NEXT: # %bb.1:
66-
; RV32-NEXT: li a0, 38
67-
; RV32-NEXT: ret
68-
; RV32-NEXT: .LBB3_2:
69-
; RV32-NEXT: li a0, 6
70-
; RV32-NEXT: ret
66+
; RV32I-LABEL: select_const_int_harder:
67+
; RV32I: # %bb.0:
68+
; RV32I-NEXT: bnez a0, .LBB3_2
69+
; RV32I-NEXT: # %bb.1:
70+
; RV32I-NEXT: li a0, 38
71+
; RV32I-NEXT: ret
72+
; RV32I-NEXT: .LBB3_2:
73+
; RV32I-NEXT: li a0, 6
74+
; RV32I-NEXT: ret
7175
;
72-
; RV64-LABEL: select_const_int_harder:
73-
; RV64: # %bb.0:
74-
; RV64-NEXT: bnez a0, .LBB3_2
75-
; RV64-NEXT: # %bb.1:
76-
; RV64-NEXT: li a0, 38
77-
; RV64-NEXT: ret
78-
; RV64-NEXT: .LBB3_2:
79-
; RV64-NEXT: li a0, 6
80-
; RV64-NEXT: ret
76+
; RV32IF-LABEL: select_const_int_harder:
77+
; RV32IF: # %bb.0:
78+
; RV32IF-NEXT: bnez a0, .LBB3_2
79+
; RV32IF-NEXT: # %bb.1:
80+
; RV32IF-NEXT: li a0, 38
81+
; RV32IF-NEXT: ret
82+
; RV32IF-NEXT: .LBB3_2:
83+
; RV32IF-NEXT: li a0, 6
84+
; RV32IF-NEXT: ret
85+
;
86+
; RV32ZICOND-LABEL: select_const_int_harder:
87+
; RV32ZICOND: # %bb.0:
88+
; RV32ZICOND-NEXT: li a1, 32
89+
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
90+
; RV32ZICOND-NEXT: addi a0, a0, 6
91+
; RV32ZICOND-NEXT: ret
92+
;
93+
; RV64I-LABEL: select_const_int_harder:
94+
; RV64I: # %bb.0:
95+
; RV64I-NEXT: bnez a0, .LBB3_2
96+
; RV64I-NEXT: # %bb.1:
97+
; RV64I-NEXT: li a0, 38
98+
; RV64I-NEXT: ret
99+
; RV64I-NEXT: .LBB3_2:
100+
; RV64I-NEXT: li a0, 6
101+
; RV64I-NEXT: ret
102+
;
103+
; RV64IFD-LABEL: select_const_int_harder:
104+
; RV64IFD: # %bb.0:
105+
; RV64IFD-NEXT: bnez a0, .LBB3_2
106+
; RV64IFD-NEXT: # %bb.1:
107+
; RV64IFD-NEXT: li a0, 38
108+
; RV64IFD-NEXT: ret
109+
; RV64IFD-NEXT: .LBB3_2:
110+
; RV64IFD-NEXT: li a0, 6
111+
; RV64IFD-NEXT: ret
112+
;
113+
; RV64ZICOND-LABEL: select_const_int_harder:
114+
; RV64ZICOND: # %bb.0:
115+
; RV64ZICOND-NEXT: li a1, 32
116+
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
117+
; RV64ZICOND-NEXT: addi a0, a0, 6
118+
; RV64ZICOND-NEXT: ret
81119
%1 = select i1 %a, i32 6, i32 38
82120
ret i32 %1
83121
}
@@ -106,6 +144,14 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
106144
; RV32IF-NEXT: fmv.x.w a0, fa5
107145
; RV32IF-NEXT: ret
108146
;
147+
; RV32ZICOND-LABEL: select_const_fp:
148+
; RV32ZICOND: # %bb.0:
149+
; RV32ZICOND-NEXT: lui a1, 1024
150+
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
151+
; RV32ZICOND-NEXT: lui a1, 263168
152+
; RV32ZICOND-NEXT: add a0, a0, a1
153+
; RV32ZICOND-NEXT: ret
154+
;
109155
; RV64I-LABEL: select_const_fp:
110156
; RV64I: # %bb.0:
111157
; RV64I-NEXT: mv a1, a0
@@ -128,6 +174,14 @@ define float @select_const_fp(i1 zeroext %a) nounwind {
128174
; RV64IFD-NEXT: fmv.w.x fa5, a0
129175
; RV64IFD-NEXT: fmv.x.w a0, fa5
130176
; RV64IFD-NEXT: ret
177+
;
178+
; RV64ZICOND-LABEL: select_const_fp:
179+
; RV64ZICOND: # %bb.0:
180+
; RV64ZICOND-NEXT: lui a1, 1024
181+
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
182+
; RV64ZICOND-NEXT: lui a1, 263168
183+
; RV64ZICOND-NEXT: add a0, a0, a1
184+
; RV64ZICOND-NEXT: ret
131185
%1 = select i1 %a, float 3.0, float 4.0
132186
ret float %1
133187
}
@@ -391,38 +445,98 @@ define i32 @select_ne_10001_10002(i32 signext %a, i32 signext %b) {
391445
}
392446

393447
define i32 @select_slt_zero_constant1_constant2(i32 signext %x) {
394-
; RV32-LABEL: select_slt_zero_constant1_constant2:
395-
; RV32: # %bb.0:
396-
; RV32-NEXT: srai a0, a0, 31
397-
; RV32-NEXT: andi a0, a0, 10
398-
; RV32-NEXT: addi a0, a0, -3
399-
; RV32-NEXT: ret
448+
; RV32I-LABEL: select_slt_zero_constant1_constant2:
449+
; RV32I: # %bb.0:
450+
; RV32I-NEXT: srai a0, a0, 31
451+
; RV32I-NEXT: andi a0, a0, 10
452+
; RV32I-NEXT: addi a0, a0, -3
453+
; RV32I-NEXT: ret
400454
;
401-
; RV64-LABEL: select_slt_zero_constant1_constant2:
402-
; RV64: # %bb.0:
403-
; RV64-NEXT: srai a0, a0, 63
404-
; RV64-NEXT: andi a0, a0, 10
405-
; RV64-NEXT: addi a0, a0, -3
406-
; RV64-NEXT: ret
455+
; RV32IF-LABEL: select_slt_zero_constant1_constant2:
456+
; RV32IF: # %bb.0:
457+
; RV32IF-NEXT: srai a0, a0, 31
458+
; RV32IF-NEXT: andi a0, a0, 10
459+
; RV32IF-NEXT: addi a0, a0, -3
460+
; RV32IF-NEXT: ret
461+
;
462+
; RV32ZICOND-LABEL: select_slt_zero_constant1_constant2:
463+
; RV32ZICOND: # %bb.0:
464+
; RV32ZICOND-NEXT: slti a0, a0, 0
465+
; RV32ZICOND-NEXT: li a1, -10
466+
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
467+
; RV32ZICOND-NEXT: addi a0, a0, 7
468+
; RV32ZICOND-NEXT: ret
469+
;
470+
; RV64I-LABEL: select_slt_zero_constant1_constant2:
471+
; RV64I: # %bb.0:
472+
; RV64I-NEXT: srai a0, a0, 63
473+
; RV64I-NEXT: andi a0, a0, 10
474+
; RV64I-NEXT: addi a0, a0, -3
475+
; RV64I-NEXT: ret
476+
;
477+
; RV64IFD-LABEL: select_slt_zero_constant1_constant2:
478+
; RV64IFD: # %bb.0:
479+
; RV64IFD-NEXT: srai a0, a0, 63
480+
; RV64IFD-NEXT: andi a0, a0, 10
481+
; RV64IFD-NEXT: addi a0, a0, -3
482+
; RV64IFD-NEXT: ret
483+
;
484+
; RV64ZICOND-LABEL: select_slt_zero_constant1_constant2:
485+
; RV64ZICOND: # %bb.0:
486+
; RV64ZICOND-NEXT: slti a0, a0, 0
487+
; RV64ZICOND-NEXT: li a1, -10
488+
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
489+
; RV64ZICOND-NEXT: addi a0, a0, 7
490+
; RV64ZICOND-NEXT: ret
407491
%cmp = icmp slt i32 %x, 0
408492
%cond = select i1 %cmp, i32 7, i32 -3
409493
ret i32 %cond
410494
}
411495

412496
define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) {
413-
; RV32-LABEL: select_sgt_negative_one_constant1_constant2:
414-
; RV32: # %bb.0:
415-
; RV32-NEXT: srai a0, a0, 31
416-
; RV32-NEXT: andi a0, a0, -10
417-
; RV32-NEXT: addi a0, a0, 7
418-
; RV32-NEXT: ret
497+
; RV32I-LABEL: select_sgt_negative_one_constant1_constant2:
498+
; RV32I: # %bb.0:
499+
; RV32I-NEXT: srai a0, a0, 31
500+
; RV32I-NEXT: andi a0, a0, -10
501+
; RV32I-NEXT: addi a0, a0, 7
502+
; RV32I-NEXT: ret
419503
;
420-
; RV64-LABEL: select_sgt_negative_one_constant1_constant2:
421-
; RV64: # %bb.0:
422-
; RV64-NEXT: srai a0, a0, 63
423-
; RV64-NEXT: andi a0, a0, -10
424-
; RV64-NEXT: addi a0, a0, 7
425-
; RV64-NEXT: ret
504+
; RV32IF-LABEL: select_sgt_negative_one_constant1_constant2:
505+
; RV32IF: # %bb.0:
506+
; RV32IF-NEXT: srai a0, a0, 31
507+
; RV32IF-NEXT: andi a0, a0, -10
508+
; RV32IF-NEXT: addi a0, a0, 7
509+
; RV32IF-NEXT: ret
510+
;
511+
; RV32ZICOND-LABEL: select_sgt_negative_one_constant1_constant2:
512+
; RV32ZICOND: # %bb.0:
513+
; RV32ZICOND-NEXT: slti a0, a0, 0
514+
; RV32ZICOND-NEXT: li a1, -10
515+
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
516+
; RV32ZICOND-NEXT: addi a0, a0, 7
517+
; RV32ZICOND-NEXT: ret
518+
;
519+
; RV64I-LABEL: select_sgt_negative_one_constant1_constant2:
520+
; RV64I: # %bb.0:
521+
; RV64I-NEXT: srai a0, a0, 63
522+
; RV64I-NEXT: andi a0, a0, -10
523+
; RV64I-NEXT: addi a0, a0, 7
524+
; RV64I-NEXT: ret
525+
;
526+
; RV64IFD-LABEL: select_sgt_negative_one_constant1_constant2:
527+
; RV64IFD: # %bb.0:
528+
; RV64IFD-NEXT: srai a0, a0, 63
529+
; RV64IFD-NEXT: andi a0, a0, -10
530+
; RV64IFD-NEXT: addi a0, a0, 7
531+
; RV64IFD-NEXT: ret
532+
;
533+
; RV64ZICOND-LABEL: select_sgt_negative_one_constant1_constant2:
534+
; RV64ZICOND: # %bb.0:
535+
; RV64ZICOND-NEXT: slti a0, a0, 0
536+
; RV64ZICOND-NEXT: li a1, -10
537+
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
538+
; RV64ZICOND-NEXT: addi a0, a0, 7
539+
; RV64ZICOND-NEXT: ret
426540
%cmp = icmp sgt i32 %x, -1
427541
%cond = select i1 %cmp, i32 7, i32 -3
428542
ret i32 %cond

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