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[TLI][TTI] Add a scalable immediate parameter to isLegalAddImmediate
1 parent c4979c9 commit dd3e5f3

19 files changed

+42
-26
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -694,7 +694,7 @@ class TargetTransformInfo {
694694
/// Return true if the specified immediate is legal add immediate, that
695695
/// is the target has add instructions which can add a register with the
696696
/// immediate without having to materialize the immediate into a register.
697-
bool isLegalAddImmediate(int64_t Imm) const;
697+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm = 0) const;
698698

699699
/// Return true if the specified immediate is legal icmp immediate,
700700
/// that is the target has icmp instructions which can compare a register
@@ -1834,7 +1834,7 @@ class TargetTransformInfo::Concept {
18341834
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3,
18351835
std::function<void(Instruction *, unsigned, APInt, APInt &)>
18361836
SimplifyAndSetOp) = 0;
1837-
virtual bool isLegalAddImmediate(int64_t Imm) = 0;
1837+
virtual bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm) = 0;
18381838
virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
18391839
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
18401840
int64_t BaseOffset, bool HasBaseReg,
@@ -2292,8 +2292,8 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
22922292
IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
22932293
SimplifyAndSetOp);
22942294
}
2295-
bool isLegalAddImmediate(int64_t Imm) override {
2296-
return Impl.isLegalAddImmediate(Imm);
2295+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm) override {
2296+
return Impl.isLegalAddImmediate(Imm, ScalableImm);
22972297
}
22982298
bool isLegalICmpImmediate(int64_t Imm) override {
22992299
return Impl.isLegalICmpImmediate(Imm);

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,9 @@ class TargetTransformInfoImplBase {
214214
void getPeelingPreferences(Loop *, ScalarEvolution &,
215215
TTI::PeelingPreferences &) const {}
216216

217-
bool isLegalAddImmediate(int64_t Imm) const { return false; }
217+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm) const {
218+
return false;
219+
}
218220

219221
bool isLegalICmpImmediate(int64_t Imm) const { return false; }
220222

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -324,8 +324,8 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
324324
return nullptr;
325325
}
326326

327-
bool isLegalAddImmediate(int64_t imm) {
328-
return getTLI()->isLegalAddImmediate(imm);
327+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm) {
328+
return getTLI()->isLegalAddImmediate(Imm, ScalableImm);
329329
}
330330

331331
bool isLegalICmpImmediate(int64_t imm) {

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2766,8 +2766,8 @@ class TargetLoweringBase {
27662766
/// Return true if the specified immediate is legal add immediate, that is the
27672767
/// target has add instructions which can add a register with the immediate
27682768
/// without having to materialize the immediate into a register.
2769-
virtual bool isLegalAddImmediate(int64_t) const {
2770-
return true;
2769+
virtual bool isLegalAddImmediate(int64_t, int64_t ScalableImm = 0) const {
2770+
return !ScalableImm;
27712771
}
27722772

27732773
/// Return true if the specified immediate is legal for the value input of a

‎llvm/lib/Analysis/TargetTransformInfo.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -391,8 +391,9 @@ void TargetTransformInfo::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
391391
return TTIImpl->getPeelingPreferences(L, SE, PP);
392392
}
393393

394-
bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
395-
return TTIImpl->isLegalAddImmediate(Imm);
394+
bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm,
395+
int64_t ScalableImm) const {
396+
return TTIImpl->isLegalAddImmediate(Imm, ScalableImm);
396397
}
397398

398399
bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16559,7 +16559,11 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
1655916559
}
1656016560

1656116561
// 12-bit optionally shifted immediates are legal for adds.
16562-
bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
16562+
bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed,
16563+
int64_t ScalableImm) const {
16564+
if (ScalableImm)
16565+
return false;
16566+
1656316567
if (Immed == std::numeric_limits<int64_t>::min()) {
1656416568
LLVM_DEBUG(dbgs() << "Illegal add imm " << Immed
1656516569
<< ": avoid UB for INT64_MIN\n");

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -688,7 +688,7 @@ class AArch64TargetLowering : public TargetLowering {
688688
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
689689
StoreInst *SI) const override;
690690

691-
bool isLegalAddImmediate(int64_t) const override;
691+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm = 0) const override;
692692
bool isLegalICmpImmediate(int64_t) const override;
693693

694694
bool isMulAddWithConstProfitable(SDValue AddNode,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19722,7 +19722,8 @@ bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1972219722
/// *or sub* immediate, that is the target has add or sub instructions which can
1972319723
/// add a register with the immediate without having to materialize the
1972419724
/// immediate into a register.
19725-
bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
19725+
bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm,
19726+
int64_t ScalableImm) const {
1972619727
// Same encoding for add/sub, just flip the sign.
1972719728
int64_t AbsImm = std::abs(Imm);
1972819729
if (!Subtarget->isThumb())

‎llvm/lib/Target/ARM/ARMISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,8 @@ class VectorType;
494494
/// add immediate, that is the target has add instructions which can
495495
/// add a register and the immediate without having to materialize
496496
/// the immediate into a register.
497-
bool isLegalAddImmediate(int64_t Imm) const override;
497+
bool isLegalAddImmediate(int64_t Imm,
498+
int64_t ScalableImm = 0) const override;
498499

499500
/// getPreIndexedAddressParts - returns true by value, base pointer and
500501
/// offset pointer and addressing mode by reference if the node's address

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4933,7 +4933,8 @@ bool LoongArchTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
49334933
return isInt<12>(Imm);
49344934
}
49354935

4936-
bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm) const {
4936+
bool LoongArchTargetLowering::isLegalAddImmediate(int64_t Imm,
4937+
int64_t ScalableImm) const {
49374938
return isInt<12>(Imm);
49384939
}
49394940

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ class LoongArchTargetLowering : public TargetLowering {
222222
Instruction *I = nullptr) const override;
223223

224224
bool isLegalICmpImmediate(int64_t Imm) const override;
225-
bool isLegalAddImmediate(int64_t Imm) const override;
225+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm = 0) const override;
226226
bool isZExtFree(SDValue Val, EVT VT2) const override;
227227
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
228228

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17300,7 +17300,8 @@ bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1730017300
return isInt<16>(Imm) || isUInt<16>(Imm);
1730117301
}
1730217302

17303-
bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
17303+
bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm,
17304+
int64_t ScalableImm) const {
1730417305
return isInt<16>(Imm) || isUInt<16>(Imm);
1730517306
}
1730617307

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1023,7 +1023,8 @@ namespace llvm {
10231023
/// add immediate, that is the target has add instructions which can
10241024
/// add a register and the immediate without having to materialize
10251025
/// the immediate into a register.
1026-
bool isLegalAddImmediate(int64_t Imm) const override;
1026+
bool isLegalAddImmediate(int64_t Imm,
1027+
int64_t ScalableImm = 0) const override;
10271028

10281029
/// isTruncateFree - Return true if it's free to truncate a value of
10291030
/// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1783,8 +1783,9 @@ bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17831783
return isInt<12>(Imm);
17841784
}
17851785

1786-
bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
1787-
return isInt<12>(Imm);
1786+
bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm,
1787+
int64_t ScalableImm) const {
1788+
return !ScalableImm && isInt<12>(Imm);
17881789
}
17891790

17901791
// On RV32, 64-bit integers are split into their high and low parts and held

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -475,7 +475,7 @@ class RISCVTargetLowering : public TargetLowering {
475475
unsigned AS,
476476
Instruction *I = nullptr) const override;
477477
bool isLegalICmpImmediate(int64_t Imm) const override;
478-
bool isLegalAddImmediate(int64_t Imm) const override;
478+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm = 0) const override;
479479
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
480480
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
481481
bool isZExtFree(SDValue Val, EVT VT2) const override;

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -944,7 +944,8 @@ bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
944944
return isInt<32>(Imm) || isUInt<32>(Imm);
945945
}
946946

947-
bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
947+
bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm,
948+
int64_t ScalableImm) const {
948949
// We can use ALGFI or SLGFI.
949950
return isUInt<32>(Imm) || isUInt<32>(-Imm);
950951
}

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,7 @@ class SystemZTargetLowering : public TargetLowering {
477477
AtomicExpansionKind
478478
shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override;
479479
bool isLegalICmpImmediate(int64_t Imm) const override;
480-
bool isLegalAddImmediate(int64_t Imm) const override;
480+
bool isLegalAddImmediate(int64_t Imm, int64_t ScalableImm = 0) const override;
481481
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
482482
unsigned AS,
483483
Instruction *I = nullptr) const override;

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33882,7 +33882,8 @@ bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3388233882
return isInt<32>(Imm);
3388333883
}
3388433884

33885-
bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
33885+
bool X86TargetLowering::isLegalAddImmediate(int64_t Imm,
33886+
int64_t ScalableImm) const {
3388633887
// Can also use sub to handle negated immediates.
3388733888
return isInt<32>(Imm);
3388833889
}

‎llvm/lib/Target/X86/X86ISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1329,7 +1329,8 @@ namespace llvm {
13291329
/// add immediate, that is the target has add instructions which can
13301330
/// add a register and the immediate without having to materialize
13311331
/// the immediate into a register.
1332-
bool isLegalAddImmediate(int64_t Imm) const override;
1332+
bool isLegalAddImmediate(int64_t Imm,
1333+
int64_t ScalableImm = 0) const override;
13331334

13341335
bool isLegalStoreImmediate(int64_t Imm) const override;
13351336

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