[AArch64] Add support for Armv9.6-A FEAT_MPAM system registers (#111822)

Add support for Armv9.6-A FEAT_MPAM system registers as documented here:

https://developer.arm.com/documentation/ddi0601/2024-09/AArch64-Registers

Author: jthackray

llvm/lib/Target/AArch64/AArch64SystemOperands.td

@@ -1970,3 +1970,14 @@ def : RWSysReg<"HACDBSCONS_EL2",    0b11, 0b100, 0b0010, 0b0011, 0b101>;
 // v9.5a Fine Grained Write Trap EL3 (FEAT_FGWTE3)
 //                                  Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"FGWTE3_EL3",        0b11, 0b110, 0b0001, 0b0001, 0b101>;
+
+// v9.6a Memory partitioning and monitoring (FEAT_MPAM) registers
+//                                        Op0   Op1    CRn     CRm     Op2
+def : ROSysReg<"MPAMBWIDR_EL1",           0b11, 0b000, 0b1010, 0b0100, 0b101>;
+def : RWSysReg<"MPAMBW3_EL3",             0b11, 0b110, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW2_EL2",             0b11, 0b100, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL1",             0b11, 0b000, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW1_EL12",            0b11, 0b101, 0b1010, 0b0101, 0b100>;
+def : RWSysReg<"MPAMBW0_EL1",             0b11, 0b000, 0b1010, 0b0101, 0b101>;
+def : RWSysReg<"MPAMBWCAP_EL2",           0b11, 0b100, 0b1010, 0b0101, 0b110>;
+def : RWSysReg<"MPAMBWSM_EL1",            0b11, 0b000, 0b1010, 0b0101, 0b111>;

llvm/test/MC/AArch64/armv9.6a-mpam.s

@@ -0,0 +1,45 @@
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK
+// RUN: FileCheck --check-prefix=CHECK-RO < %t %s
+
+//------------------------------------------------------------------------------
+// Armv9.6-A FEAT_MPAM Extensions
+//------------------------------------------------------------------------------
+
+msr MPAMBWIDR_EL1, x0
+msr MPAMBW3_EL3, x0
+msr MPAMBW2_EL2, x0
+msr MPAMBW1_EL1, x0
+msr MPAMBW1_EL12, x0
+msr MPAMBW0_EL1, x0
+msr MPAMBWCAP_EL2, x0
+msr MPAMBWSM_EL1, x0
+
+mrs x0, MPAMBWIDR_EL1
+mrs x0, MPAMBW3_EL3
+mrs x0, MPAMBW2_EL2
+mrs x0, MPAMBW1_EL1
+mrs x0, MPAMBW1_EL12
+mrs x0, MPAMBW0_EL1
+mrs x0, MPAMBWCAP_EL2
+mrs x0, MPAMBWSM_EL1
+
+//CHECK: msr     MPAMBW3_EL3, x0                 // encoding: [0x80,0xa5,0x1e,0xd5]
+//CHECK: msr     MPAMBW2_EL2, x0                 // encoding: [0x80,0xa5,0x1c,0xd5]
+//CHECK: msr     MPAMBW1_EL1, x0                 // encoding: [0x80,0xa5,0x18,0xd5]
+//CHECK: msr     MPAMBW1_EL12, x0                // encoding: [0x80,0xa5,0x1d,0xd5]
+//CHECK: msr     MPAMBW0_EL1, x0                 // encoding: [0xa0,0xa5,0x18,0xd5]
+//CHECK: msr     MPAMBWCAP_EL2, x0               // encoding: [0xc0,0xa5,0x1c,0xd5]
+//CHECK: msr     MPAMBWSM_EL1, x0                // encoding: [0xe0,0xa5,0x18,0xd5]
+
+//CHECK-RO: error: expected writable system register or pstate
+//CHECK-RO: msr MPAMBWIDR_EL1, x0
+//CHECK-RO:     ^
+
+//CHECK: mrs     x0, MPAMBWIDR_EL1               // encoding: [0xa0,0xa4,0x38,0xd5]
+//CHECK: mrs     x0, MPAMBW3_EL3                 // encoding: [0x80,0xa5,0x3e,0xd5]
+//CHECK: mrs     x0, MPAMBW2_EL2                 // encoding: [0x80,0xa5,0x3c,0xd5]
+//CHECK: mrs     x0, MPAMBW1_EL1                 // encoding: [0x80,0xa5,0x38,0xd5]
+//CHECK: mrs     x0, MPAMBW1_EL12                // encoding: [0x80,0xa5,0x3d,0xd5]
+//CHECK: mrs     x0, MPAMBW0_EL1                 // encoding: [0xa0,0xa5,0x38,0xd5]
+//CHECK: mrs     x0, MPAMBWCAP_EL2               // encoding: [0xc0,0xa5,0x3c,0xd5]
+//CHECK: mrs     x0, MPAMBWSM_EL1                // encoding: [0xe0,0xa5,0x38,0xd5]

llvm/test/MC/Disassembler/AArch64/armv9.6a-mpam.txt

@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s
+
+#------------------------------------------------------------------------------
+# Armv9.6-A FEAT_MPAM Extensions
+#------------------------------------------------------------------------------
+
+[0x80,0xa5,0x1e,0xd5]
+# CHECK: msr MPAMBW3_EL3, x0
+
+[0x80,0xa5,0x1c,0xd5]
+# CHECK: msr MPAMBW2_EL2, x0
+
+[0x80,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBW1_EL1, x0
+
+[0x80,0xa5,0x1d,0xd5]
+# CHECK: msr MPAMBW1_EL12, x0
+
+[0xa0,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBW0_EL1, x0
+
+[0xc0,0xa5,0x1c,0xd5]
+# CHECK: msr MPAMBWCAP_EL2, x0
+
+[0xe0,0xa5,0x18,0xd5]
+# CHECK: msr MPAMBWSM_EL1, x0
+
+[0xa0,0xa4,0x38,0xd5]
+# CHECK: mrs x0, MPAMBWIDR_EL1
+
+[0x80,0xa5,0x3e,0xd5]
+# CHECK: mrs x0, MPAMBW3_EL3
+
+[0x80,0xa5,0x3c,0xd5]
+# CHECK: mrs x0, MPAMBW2_EL2
+
+[0x80,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBW1_EL1
+
+[0x80,0xa5,0x3d,0xd5]
+# CHECK: mrs x0, MPAMBW1_EL12
+
+[0xa0,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBW0_EL1
+
+[0xc0,0xa5,0x3c,0xd5]
+# CHECK: mrs x0, MPAMBWCAP_EL2
+
+[0xe0,0xa5,0x38,0xd5]
+# CHECK: mrs x0, MPAMBWSM_EL1