Skip to content

Commit ddba6b2

Browse files
jayfoadjayfoad
authored
[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (#82233)
64-bit SDWA encodings have to be checked first because their first 32 bits are a special case of the corresponding 32-bit non-SDWA encoding of the same instruction. But all 64-bit encodings are checked first, so we don't need special handling for SDWA.
1 parent d5922cf commit ddba6b2

File tree

4 files changed

+36
-61
lines changed

4 files changed

+36
-61
lines changed

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 1 addition & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -457,8 +457,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
457457
ArrayRef<uint8_t> Bytes_,
458458
uint64_t Address,
459459
raw_ostream &CS) const {
460-
bool IsSDWA = false;
461-
462460
unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
463461
Bytes = Bytes_.slice(0, MaxInstBytesNum);
464462

@@ -572,15 +570,6 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
572570
break;
573571
}
574572

575-
Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS);
576-
if (Res) { IsSDWA = true; break; }
577-
578-
Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS);
579-
if (Res) { IsSDWA = true; break; }
580-
581-
Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS);
582-
if (Res) { IsSDWA = true; break; }
583-
584573
if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
585574
Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS);
586575
if (Res)
@@ -771,7 +760,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
771760
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP))
772761
Res = convertVINTERPInst(MI);
773762

774-
if (Res && IsSDWA)
763+
if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA))
775764
Res = convertSDWAInst(MI);
776765

777766
int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -985,15 +985,11 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
985985
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
986986
def _sdwa_gfx10 :
987987
VOP_SDWA10_Real<!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
988-
VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
989-
let DecoderNamespace = "SDWA10";
990-
}
988+
VOP1_SDWA9Ae<op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
991989
}
992990
multiclass VOP1_Real_dpp_gfx10<bits<9> op> {
993991
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
994-
def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> {
995-
let DecoderNamespace = "SDWA10";
996-
}
992+
def _dpp_gfx10 : VOP1_DPP16<op{7-0}, !cast<VOP1_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
997993
}
998994
multiclass VOP1_Real_dpp8_gfx10<bits<9> op> {
999995
if !cast<VOP1_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then

‎llvm/lib/Target/AMDGPU/VOP2Instructions.td

Lines changed: 30 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1740,15 +1740,11 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
17401740
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtSDWA9 then
17411741
def _sdwa_gfx10 :
17421742
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
1743-
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl> {
1744-
let DecoderNamespace = "SDWA10";
1745-
}
1743+
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
17461744
}
17471745
multiclass VOP2_Real_dpp_gfx10<bits<6> op> {
17481746
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
1749-
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10> {
1750-
let DecoderNamespace = "SDWA10";
1751-
}
1747+
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX10>;
17521748
}
17531749
multiclass VOP2_Real_dpp8_gfx10<bits<6> op> {
17541750
if !cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExt32BitDPP then
@@ -1777,35 +1773,33 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
17771773
let AsmString = asmName # ps.AsmOperands;
17781774
}
17791775
}
1780-
let DecoderNamespace = "SDWA10" in {
1781-
multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1782-
string asmName> {
1783-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
1784-
def _sdwa_gfx10 :
1785-
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1786-
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1787-
VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1788-
let AsmString = asmName # ps.AsmOperands;
1789-
}
1790-
}
1791-
multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1792-
string asmName> {
1793-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
1794-
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> {
1795-
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1796-
let AsmString = asmName # ps.Pfl.AsmDPP16;
1776+
multiclass VOP2_Real_sdwa_gfx10_with_name<bits<6> op, string opName,
1777+
string asmName> {
1778+
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
1779+
def _sdwa_gfx10 :
1780+
VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
1781+
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
1782+
VOP2_SDWA_Pseudo ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
1783+
let AsmString = asmName # ps.AsmOperands;
17971784
}
1785+
}
1786+
multiclass VOP2_Real_dpp_gfx10_with_name<bits<6> op, string opName,
1787+
string asmName> {
1788+
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
1789+
def _dpp_gfx10 : VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10> {
1790+
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1791+
let AsmString = asmName # ps.Pfl.AsmDPP16;
17981792
}
1799-
multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1800-
string asmName> {
1801-
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
1802-
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1803-
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1804-
let AsmString = asmName # ps.Pfl.AsmDPP8;
1805-
let DecoderNamespace = "DPP8";
1806-
}
1793+
}
1794+
multiclass VOP2_Real_dpp8_gfx10_with_name<bits<6> op, string opName,
1795+
string asmName> {
1796+
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
1797+
def _dpp8_gfx10 : VOP2_DPP8<op, !cast<VOP2_Pseudo>(opName#"_e32")> {
1798+
VOP2_Pseudo ps = !cast<VOP2_Pseudo>(opName#"_e32");
1799+
let AsmString = asmName # ps.Pfl.AsmDPP8;
1800+
let DecoderNamespace = "DPP8";
18071801
}
1808-
} // End DecoderNamespace = "SDWA10"
1802+
}
18091803

18101804
//===------------------------------ VOP2be ------------------------------===//
18111805
multiclass VOP2be_Real_e32_gfx10<bits<6> op, string opName, string asmName> {
@@ -1832,7 +1826,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
18321826
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
18331827
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
18341828
let AsmString = asmName # !subst(", vcc", "", Ps.AsmOperands);
1835-
let DecoderNamespace = "SDWA10";
18361829
}
18371830
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
18381831
def _sdwa_w32_gfx10 :
@@ -1841,17 +1834,15 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
18411834
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
18421835
let AsmString = asmName # !subst("vcc", "vcc_lo", Ps.AsmOperands);
18431836
let isAsmParserOnly = 1;
1844-
let DecoderNamespace = "SDWA10";
18451837
let WaveSizePredicate = isWave32;
1846-
}
1838+
}
18471839
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExtSDWA9 then
18481840
def _sdwa_w64_gfx10 :
18491841
Base_VOP_SDWA10_Real<!cast<VOP2_SDWA_Pseudo>(opName#"_sdwa")>,
18501842
VOP2_SDWA9Ae<op{5-0}, !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa").Pfl> {
18511843
VOP2_SDWA_Pseudo Ps = !cast<VOP2_SDWA_Pseudo>(opName#"_sdwa");
18521844
let AsmString = asmName # Ps.AsmOperands;
18531845
let isAsmParserOnly = 1;
1854-
let DecoderNamespace = "SDWA10";
18551846
let WaveSizePredicate = isWave64;
18561847
}
18571848
}
@@ -1861,7 +1852,6 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10" in {
18611852
VOP2_DPP16<op, !cast<VOP2_DPP_Pseudo>(opName#"_dpp"), SIEncodingFamily.GFX10, asmName> {
18621853
string AsmDPP = !cast<VOP2_Pseudo>(opName#"_e32").Pfl.AsmDPP16;
18631854
let AsmString = asmName # !subst(", vcc", "", AsmDPP);
1864-
let DecoderNamespace = "SDWA10";
18651855
}
18661856
if !cast<VOP2_Pseudo>(opName#"_e32").Pfl.HasExt32BitDPP then
18671857
def _dpp_w32_gfx10 :
@@ -2305,7 +2295,7 @@ multiclass VOP2be_Real_e32e64_gfx9 <bits<6> op, string OpName, string AsmName> {
23052295
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(OpName#"_dpp")> {
23062296
VOP2_DPP_Pseudo ps = !cast<VOP2_DPP_Pseudo>(OpName#"_dpp");
23072297
let AsmString = AsmName # ps.AsmOperands;
2308-
let DecoderNamespace = "SDWA9";
2298+
let DecoderNamespace = "GFX9";
23092299
}
23102300
}
23112301

@@ -2329,7 +2319,7 @@ multiclass VOP2_Real_e32e64_gfx9 <bits<6> op> {
23292319
def _dpp_gfx9 :
23302320
VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX9>,
23312321
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
2332-
let DecoderNamespace = "SDWA9";
2322+
let DecoderNamespace = "GFX9";
23332323
}
23342324
}
23352325

@@ -2489,7 +2479,7 @@ let AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A" in {
24892479
def _dpp_gfx90a :
24902480
VOP_DPP_Real<!cast<VOP2_DPP_Pseudo>(NAME#"_dpp"), SIEncodingFamily.GFX90A>,
24912481
VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
2492-
let DecoderNamespace = "SDWA9";
2482+
let DecoderNamespace = "GFX9";
24932483
}
24942484
}
24952485
} // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"

‎llvm/lib/Target/AMDGPU/VOPInstructions.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -616,7 +616,7 @@ class VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
616616
let AssemblerPredicate = HasSDWA;
617617
let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
618618
AMDGPUAsmVariants.Disable);
619-
let DecoderNamespace = "SDWA";
619+
let DecoderNamespace = "GFX8";
620620

621621
VOPProfile Pfl = P;
622622
}
@@ -672,7 +672,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
672672
let AssemblerPredicate = HasSDWA9;
673673
let AsmVariantName = !if(ps.Pfl.HasExtSDWA9, AMDGPUAsmVariants.SDWA9,
674674
AMDGPUAsmVariants.Disable);
675-
let DecoderNamespace = "SDWA9";
675+
let DecoderNamespace = "GFX9";
676676

677677
// Copy relevant pseudo op flags
678678
let AsmMatchConverter = ps.AsmMatchConverter;
@@ -693,7 +693,7 @@ class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
693693
class Base_VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> : Base_VOP_SDWA9_Real<ps> {
694694
let SubtargetPredicate = HasSDWA10;
695695
let AssemblerPredicate = HasSDWA10;
696-
let DecoderNamespace = "SDWA10";
696+
let DecoderNamespace = "GFX10";
697697
}
698698

699699
class VOP_SDWA10_Real<VOP_SDWA_Pseudo ps> :

0 commit comments

Comments
 (0)