Skip to content

Commit ddd1a4b

Browse files
committed
[InstCombine] Add Tests for Testing Bits; NFC
1 parent ee572ed commit ddd1a4b

File tree

1 file changed

+187
-0
lines changed

1 file changed

+187
-0
lines changed

llvm/test/Transforms/InstCombine/icmp-and-shift.ll

Lines changed: 187 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -738,3 +738,190 @@ define i1 @test_const_shr_and_1_ne_0_multi_use_and_negative(i32 %b) {
738738
%ret = and i1 %cmp1, %cmp2
739739
ret i1 %ret
740740
}
741+
742+
define i1 @test_shl_sub_bw_minus_1_slt_0(i32 %a, i32 %b) {
743+
; CHECK-LABEL: @test_shl_sub_bw_minus_1_slt_0(
744+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
745+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
746+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 0
747+
; CHECK-NEXT: ret i1 [[CMP]]
748+
;
749+
%sub = sub i32 31, %b
750+
%shl = shl i32 %a, %sub
751+
%cmp = icmp slt i32 %shl, 0
752+
ret i1 %cmp
753+
}
754+
755+
define i1 @test_const_shl_sub_bw_minus_1_slt_0(i32 %b) {
756+
; CHECK-LABEL: @test_const_shl_sub_bw_minus_1_slt_0(
757+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
758+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 42, [[SUB]]
759+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 0
760+
; CHECK-NEXT: ret i1 [[CMP]]
761+
;
762+
%sub = sub i32 31, %b
763+
%shl = shl i32 42, %sub
764+
%cmp = icmp slt i32 %shl, 0
765+
ret i1 %cmp
766+
}
767+
768+
define i1 @test_not_shl_sub_bw_minus_1_slt_0(i32 %a, i32 %b) {
769+
; CHECK-LABEL: @test_not_shl_sub_bw_minus_1_slt_0(
770+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
771+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
772+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SHL]], -1
773+
; CHECK-NEXT: ret i1 [[CMP]]
774+
;
775+
%sub = sub i32 31, %b
776+
%shl = shl i32 %a, %sub
777+
%cmp = icmp sge i32 %shl, 0
778+
ret i1 %cmp
779+
}
780+
781+
define i1 @test_shl_nuw_sub_bw_minus_1_slt_0(i32 %a, i32 %b) {
782+
; CHECK-LABEL: @test_shl_nuw_sub_bw_minus_1_slt_0(
783+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
784+
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 [[A:%.*]], [[SUB]]
785+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 0
786+
; CHECK-NEXT: ret i1 [[CMP]]
787+
;
788+
%sub = sub i32 31, %b
789+
%shl = shl nuw i32 %a, %sub
790+
%cmp = icmp slt i32 %shl, 0
791+
ret i1 %cmp
792+
}
793+
794+
define i1 @test_not_const_shl_sub_bw_minus_1_slt_0(i32 %b) {
795+
; CHECK-LABEL: @test_not_const_shl_sub_bw_minus_1_slt_0(
796+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
797+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 42, [[SUB]]
798+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SHL]], -1
799+
; CHECK-NEXT: ret i1 [[CMP]]
800+
;
801+
%sub = sub i32 31, %b
802+
%shl = shl i32 42, %sub
803+
%cmp = icmp sge i32 %shl, 0
804+
ret i1 %cmp
805+
}
806+
807+
define <8 x i1> @test_shl_sub_bw_minus_1_slt_0_v8i8(<8 x i8> %a, <8 x i8> %b) {
808+
; CHECK-LABEL: @test_shl_sub_bw_minus_1_slt_0_v8i8(
809+
; CHECK-NEXT: [[SUB:%.*]] = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, [[B:%.*]]
810+
; CHECK-NEXT: [[SHL:%.*]] = shl <8 x i8> [[A:%.*]], [[SUB]]
811+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i8> [[SHL]], zeroinitializer
812+
; CHECK-NEXT: ret <8 x i1> [[CMP]]
813+
;
814+
%sub = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, %b
815+
%shl = shl <8 x i8> %a, %sub
816+
%cmp = icmp slt <8 x i8> %shl, zeroinitializer
817+
ret <8 x i1> %cmp
818+
}
819+
820+
define <8 x i1> @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat(<8 x i8> %b) {
821+
; CHECK-LABEL: @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat(
822+
; CHECK-NEXT: [[SUB:%.*]] = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, [[B:%.*]]
823+
; CHECK-NEXT: [[SHL:%.*]] = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, [[SUB]]
824+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i8> [[SHL]], zeroinitializer
825+
; CHECK-NEXT: ret <8 x i1> [[CMP]]
826+
;
827+
%sub = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, %b
828+
%shl = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, %sub
829+
%cmp = icmp slt <8 x i8> %shl, zeroinitializer
830+
ret <8 x i1> %cmp
831+
}
832+
833+
define <8 x i1> @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat_poison_1(<8 x i8> %b) {
834+
; CHECK-LABEL: @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat_poison_1(
835+
; CHECK-NEXT: [[SUB:%.*]] = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 poison>, [[B:%.*]]
836+
; CHECK-NEXT: [[SHL:%.*]] = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, [[SUB]]
837+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i8> [[SHL]], zeroinitializer
838+
; CHECK-NEXT: ret <8 x i1> [[CMP]]
839+
;
840+
%sub = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 poison>, %b
841+
%shl = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42>, %sub
842+
%cmp = icmp slt <8 x i8> %shl, zeroinitializer
843+
ret <8 x i1> %cmp
844+
}
845+
846+
define <8 x i1> @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat_poison_2(<8 x i8> %b) {
847+
; CHECK-LABEL: @test_const_shl_sub_bw_minus_1_slt_0_v8i8_splat_poison_2(
848+
; CHECK-NEXT: [[SUB:%.*]] = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, [[B:%.*]]
849+
; CHECK-NEXT: [[SHL:%.*]] = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 poison>, [[SUB]]
850+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i8> [[SHL]], zeroinitializer
851+
; CHECK-NEXT: ret <8 x i1> [[CMP]]
852+
;
853+
%sub = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, %b
854+
%shl = shl <8 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 poison>, %sub
855+
%cmp = icmp slt <8 x i8> %shl, zeroinitializer
856+
ret <8 x i1> %cmp
857+
}
858+
859+
define <8 x i1> @test_const_shl_sub_bw_minus_1_slt_0_v8i8_nonsplat(<8 x i8> %b) {
860+
; CHECK-LABEL: @test_const_shl_sub_bw_minus_1_slt_0_v8i8_nonsplat(
861+
; CHECK-NEXT: [[SUB:%.*]] = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, [[B:%.*]]
862+
; CHECK-NEXT: [[SHL:%.*]] = shl <8 x i8> <i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49>, [[SUB]]
863+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <8 x i8> [[SHL]], zeroinitializer
864+
; CHECK-NEXT: ret <8 x i1> [[CMP]]
865+
;
866+
%sub = sub <8 x i8> <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>, %b
867+
%shl = shl <8 x i8> <i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49>, %sub
868+
%cmp = icmp slt <8 x i8> %shl, zeroinitializer
869+
ret <8 x i1> %cmp
870+
}
871+
872+
define i1 @test_shl_sub_non_bw_minus_1_slt_0_negative(i32 %a, i32 %b) {
873+
; CHECK-LABEL: @test_shl_sub_non_bw_minus_1_slt_0_negative(
874+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 32, [[B:%.*]]
875+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
876+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[SHL]], 0
877+
; CHECK-NEXT: ret i1 [[CMP]]
878+
;
879+
%sub = sub i32 32, %b
880+
%shl = shl i32 %a, %sub
881+
%cmp = icmp slt i32 %shl, 0
882+
ret i1 %cmp
883+
}
884+
885+
define i1 @test_shl_sub_bw_minus_1_slt_0_i1_negative(i1 %a, i1 %b) {
886+
; CHECK-LABEL: @test_shl_sub_bw_minus_1_slt_0_i1_negative(
887+
; CHECK-NEXT: ret i1 [[A:%.*]]
888+
;
889+
%sub = sub i1 0, %b
890+
%shl = shl i1 %a, %sub
891+
%cmp = icmp slt i1 %shl, 0
892+
ret i1 %cmp
893+
}
894+
895+
define i1 @test_shl_sub_bw_minus_1_slt_0_multi_use_sub_negative(i32 %a, i32 %b) {
896+
; CHECK-LABEL: @test_shl_sub_bw_minus_1_slt_0_multi_use_sub_negative(
897+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
898+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
899+
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[SHL]], 0
900+
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[SUB]], [[B]]
901+
; CHECK-NEXT: [[RET:%.*]] = or i1 [[CMP1]], [[CMP2]]
902+
; CHECK-NEXT: ret i1 [[RET]]
903+
;
904+
%sub = sub i32 31, %b
905+
%shl = shl i32 %a, %sub
906+
%cmp1 = icmp slt i32 %shl, 0
907+
%cmp2 = icmp slt i32 %b, %sub
908+
%ret = or i1 %cmp1, %cmp2
909+
ret i1 %ret
910+
}
911+
912+
define i1 @test_shl_sub_bw_minus_1_slt_0_multi_use_shl_negative(i32 %a, i32 %b) {
913+
; CHECK-LABEL: @test_shl_sub_bw_minus_1_slt_0_multi_use_shl_negative(
914+
; CHECK-NEXT: [[SUB:%.*]] = sub i32 31, [[B:%.*]]
915+
; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
916+
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[SHL]], 0
917+
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[SHL]], [[B]]
918+
; CHECK-NEXT: [[RET:%.*]] = and i1 [[CMP1]], [[CMP2]]
919+
; CHECK-NEXT: ret i1 [[RET]]
920+
;
921+
%sub = sub i32 31, %b
922+
%shl = shl i32 %a, %sub
923+
%cmp1 = icmp slt i32 %shl, 0
924+
%cmp2 = icmp eq i32 %b, %shl
925+
%ret = and i1 %cmp1, %cmp2
926+
ret i1 %ret
927+
}

0 commit comments

Comments
 (0)