Address comment, fix mask types not returning log2 EEW

Author: lukel97

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -4007,12 +4007,12 @@ unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
   return RVV->BaseInstr;
 }
 
-unsigned RISCV::getDestEEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
+unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
   unsigned DestEEW =
       (Desc.TSFlags & RISCVII::DestEEWMask) >> RISCVII::DestEEWShift;
   // EEW = 1
   if (DestEEW == 0)
-    return 1;
+    return 0;
   // EEW = SEW * n
   unsigned Scaled = Log2SEW + (DestEEW - 1);
   assert(Scaled >= 3 && Scaled <= 6);

llvm/lib/Target/RISCV/RISCVInstrInfo.h

@@ -355,8 +355,8 @@ std::optional<unsigned> getVectorLowDemandedScalarBits(uint16_t Opcode,
 unsigned getRVVMCOpcode(unsigned RVVPseudoOpcode);
 
 // For a (non-pseudo) RVV instruction \p Desc and the given \p Log2SEW, returns
-// the EEW of the destination operand.
-unsigned getDestEEW(const MCInstrDesc &Desc, unsigned Log2SEW);
+// the log2 EEW of the destination operand.
+unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
 
 // Special immediate for AVL operand of V pseudo instructions to indicate VLMax.
 static constexpr int64_t VLMaxSentinel = -1LL;

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -102,13 +102,13 @@ static bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
 /// operand of \p Src with an unknown EEW, return true if their EEWs match.
 bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
                                      const MachineInstr &Src) const {
-  unsigned UserSEW =
+  unsigned UserLog2SEW =
       User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
-  unsigned SrcSEW =
+  unsigned SrcLog2SEW =
       Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
-  unsigned SrcEEW = RISCV::getDestEEW(
-      TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcSEW);
-  return SrcEEW == UserSEW;
+  unsigned SrcLog2EEW = RISCV::getDestLog2EEW(
+      TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW);
+  return SrcLog2EEW == UserLog2SEW;
 }
 
 // Attempt to reduce the VL of an instruction whose sole use is feeding a

llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp

@@ -318,23 +318,23 @@ TEST_P(RISCVInstrInfoTest, DescribeLoadedValue) {
 
 TEST_P(RISCVInstrInfoTest, GetDestEEW) {
   const RISCVInstrInfo *TII = ST->getInstrInfo();
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VADD_VV), 3), 3u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VWADD_VV), 3), 4u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VLE32_V), 5), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VLSE32_V), 5), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VREDSUM_VS), 4), 4u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VWREDSUM_VS), 4), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VFWREDOSUM_VS), 5), 6u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VFCVT_RTZ_XU_F_V), 4), 4u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VFWCVT_RTZ_XU_F_V), 4), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VSLL_VI), 4), 4u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VWSLL_VI), 4), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VMSEQ_VV), 4), 1u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VMAND_MM), 0), 1u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VIOTA_M), 3), 3u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VQMACCU_2x8x2), 3), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::VFWMACC_4x4x4), 4), 5u);
-  EXPECT_EQ(RISCV::getDestEEW(TII->get(RISCV::THVdotVMAQA_VV), 5), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VADD_VV), 3), 3u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VWADD_VV), 3), 4u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VLE32_V), 5), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VLSE32_V), 5), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VREDSUM_VS), 4), 4u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VWREDSUM_VS), 4), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VFWREDOSUM_VS), 5), 6u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VFCVT_RTZ_XU_F_V), 4), 4u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VFWCVT_RTZ_XU_F_V), 4), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VSLL_VI), 4), 4u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VWSLL_VI), 4), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VMSEQ_VV), 4), 0u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VMAND_MM), 0), 0u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VIOTA_M), 3), 3u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VQMACCU_2x8x2), 3), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::VFWMACC_4x4x4), 4), 5u);
+  EXPECT_EQ(RISCV::getDestLog2EEW(TII->get(RISCV::THVdotVMAQA_VV), 5), 5u);
 }
 
 } // namespace