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[DAGCombiner] Add basic support for trunc nsw/nuw 
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5 files changed

+59
-65
lines changed

5 files changed

+59
-65
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2329,6 +2329,8 @@ static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
23292329
if (N->getOpcode() == ISD::TRUNCATE) {
23302330
Op = N->getOperand(0);
23312331
Known = DAG.computeKnownBits(Op);
2332+
if (N->getFlags().hasNoUnsignedWrap())
2333+
Known.Zero.setBitsFrom(N.getScalarValueSizeInBits());
23322334
return true;
23332335
}
23342336

@@ -13807,23 +13809,22 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1380713809
unsigned OpBits = Op.getScalarValueSizeInBits();
1380813810
unsigned MidBits = N0.getScalarValueSizeInBits();
1380913811
unsigned DestBits = VT.getScalarSizeInBits();
13810-
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
1381113812

13812-
if (OpBits == DestBits) {
13813-
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
13814-
// bits, it is already ready.
13815-
if (NumSignBits > DestBits-MidBits)
13813+
if (N0->getFlags().hasNoSignedWrap() ||
13814+
DAG.ComputeNumSignBits(Op) > OpBits - MidBits) {
13815+
if (OpBits == DestBits) {
13816+
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
13817+
// bits, it is already ready.
1381613818
return Op;
13817-
} else if (OpBits < DestBits) {
13818-
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
13819-
// bits, just sext from i32.
13820-
if (NumSignBits > OpBits-MidBits)
13819+
} else if (OpBits < DestBits) {
13820+
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
13821+
// bits, just sext from i32.
1382113822
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
13822-
} else {
13823-
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
13824-
// bits, just truncate to i32.
13825-
if (NumSignBits > OpBits-MidBits)
13823+
} else {
13824+
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
13825+
// bits, just truncate to i32.
1382613826
return DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
13827+
}
1382713828
}
1382813829

1382913830
// fold (sext (truncate x)) -> (sextinreg x).
@@ -14094,24 +14095,23 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1409414095
unsigned OpBits = SrcVT.getScalarSizeInBits();
1409514096
unsigned MidBits = MinVT.getScalarSizeInBits();
1409614097
unsigned DestBits = VT.getScalarSizeInBits();
14097-
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
1409814098

14099-
if (OpBits == DestBits) {
14100-
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
14101-
// bits, it is already ready.
14102-
if (NumSignBits > DestBits - MidBits)
14099+
if (N0->getFlags().hasNoSignedWrap() ||
14100+
DAG.ComputeNumSignBits(Op) > OpBits - MidBits) {
14101+
if (OpBits == DestBits) {
14102+
// Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
14103+
// bits, it is already ready.
1410314104
return Op;
14104-
} else if (OpBits < DestBits) {
14105-
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
14106-
// bits, just sext from i32.
14107-
// FIXME: This can probably be ZERO_EXTEND nneg?
14108-
if (NumSignBits > OpBits - MidBits)
14105+
} else if (OpBits < DestBits) {
14106+
// Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
14107+
// bits, just sext from i32.
14108+
// FIXME: This can probably be ZERO_EXTEND nneg?
1410914109
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
14110-
} else {
14111-
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
14112-
// bits, just truncate to i32.
14113-
if (NumSignBits > OpBits - MidBits)
14110+
} else {
14111+
// Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
14112+
// bits, just truncate to i32.
1411414113
return DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
14114+
}
1411514115
}
1411614116
}
1411714117

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3823,7 +3823,13 @@ void SelectionDAGBuilder::visitTrunc(const User &I) {
38233823
SDValue N = getValue(I.getOperand(0));
38243824
EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
38253825
I.getType());
3826-
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
3826+
SDNodeFlags Flags;
3827+
if (auto *Trunc = dyn_cast<TruncInst>(&I)) {
3828+
Flags.setNoSignedWrap(Trunc->hasNoSignedWrap());
3829+
Flags.setNoUnsignedWrap(Trunc->hasNoUnsignedWrap());
3830+
}
3831+
3832+
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N, Flags));
38273833
}
38283834

38293835
void SelectionDAGBuilder::visitZExt(const User &I) {

‎llvm/test/CodeGen/AArch64/trunc-nsw-nuw.ll

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,9 @@ define zeroext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
55
; CHECK-LABEL: trunc_nuw_nsw_urem:
66
; CHECK: // %bb.0: // %entry
77
; CHECK-NEXT: mov w8, #5977 // =0x1759
8-
; CHECK-NEXT: mov w9, w0
9-
; CHECK-NEXT: movk w8, #53687, lsl #16
10-
; CHECK-NEXT: umull x8, w9, w8
118
; CHECK-NEXT: mov w9, #10000 // =0x2710
9+
; CHECK-NEXT: movk w8, #53687, lsl #16
10+
; CHECK-NEXT: mul x8, x0, x8
1211
; CHECK-NEXT: lsr x8, x8, #45
1312
; CHECK-NEXT: msub w0, w8, w9, w0
1413
; CHECK-NEXT: ret
@@ -22,8 +21,7 @@ define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
2221
; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
2322
; CHECK: // %bb.0: // %entry
2423
; CHECK-NEXT: mov w8, #52429 // =0xcccd
25-
; CHECK-NEXT: and w9, w0, #0xffff
26-
; CHECK-NEXT: mul w8, w9, w8
24+
; CHECK-NEXT: mul w8, w0, w8
2725
; CHECK-NEXT: lsr w0, w8, #23
2826
; CHECK-NEXT: ret
2927
entry:
@@ -37,8 +35,7 @@ define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
3735
; CHECK-LABEL: sext_udiv_trunc_nuw:
3836
; CHECK: // %bb.0: // %entry
3937
; CHECK-NEXT: mov w8, #52429 // =0xcccd
40-
; CHECK-NEXT: and w9, w0, #0xffff
41-
; CHECK-NEXT: mul w8, w9, w8
38+
; CHECK-NEXT: mul w8, w0, w8
4239
; CHECK-NEXT: lsr w0, w8, #23
4340
; CHECK-NEXT: ret
4441
entry:

‎llvm/test/CodeGen/RISCV/trunc-nsw-nuw.ll

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,7 @@
44
define signext i8 @trunc_nsw_add(i32 signext %x) nounwind {
55
; CHECK-LABEL: trunc_nsw_add:
66
; CHECK: # %bb.0: # %entry
7-
; CHECK-NEXT: addi a0, a0, 1
8-
; CHECK-NEXT: slli a0, a0, 56
9-
; CHECK-NEXT: srai a0, a0, 56
7+
; CHECK-NEXT: addiw a0, a0, 1
108
; CHECK-NEXT: ret
119
entry:
1210
%add = add nsw i32 %x, 1
@@ -17,11 +15,11 @@ entry:
1715
define signext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
1816
; CHECK-LABEL: trunc_nuw_nsw_urem:
1917
; CHECK: # %bb.0: # %entry
20-
; CHECK-NEXT: slli a1, a0, 32
21-
; CHECK-NEXT: lui a2, 858993
22-
; CHECK-NEXT: addi a2, a2, 1881
23-
; CHECK-NEXT: slli a2, a2, 32
24-
; CHECK-NEXT: mulhu a1, a1, a2
18+
; CHECK-NEXT: lui a1, 210
19+
; CHECK-NEXT: addiw a1, a1, -1167
20+
; CHECK-NEXT: slli a1, a1, 12
21+
; CHECK-NEXT: addi a1, a1, 1881
22+
; CHECK-NEXT: mul a1, a0, a1
2523
; CHECK-NEXT: srli a1, a1, 45
2624
; CHECK-NEXT: lui a2, 2
2725
; CHECK-NEXT: addi a2, a2, 1808
@@ -37,11 +35,10 @@ entry:
3735
define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
3836
; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
3937
; CHECK: # %bb.0: # %entry
40-
; CHECK-NEXT: lui a1, 52429
41-
; CHECK-NEXT: slli a1, a1, 4
42-
; CHECK-NEXT: slli a0, a0, 48
43-
; CHECK-NEXT: mulhu a0, a0, a1
44-
; CHECK-NEXT: srli a0, a0, 23
38+
; CHECK-NEXT: lui a1, 13
39+
; CHECK-NEXT: addi a1, a1, -819
40+
; CHECK-NEXT: mul a0, a0, a1
41+
; CHECK-NEXT: srliw a0, a0, 23
4542
; CHECK-NEXT: ret
4643
entry:
4744
%trunc = trunc nuw i64 %x to i16
@@ -53,11 +50,10 @@ entry:
5350
define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
5451
; CHECK-LABEL: sext_udiv_trunc_nuw:
5552
; CHECK: # %bb.0: # %entry
56-
; CHECK-NEXT: lui a1, 52429
57-
; CHECK-NEXT: slli a1, a1, 4
58-
; CHECK-NEXT: slli a0, a0, 48
59-
; CHECK-NEXT: mulhu a0, a0, a1
60-
; CHECK-NEXT: srli a0, a0, 23
53+
; CHECK-NEXT: lui a1, 13
54+
; CHECK-NEXT: addi a1, a1, -819
55+
; CHECK-NEXT: mul a0, a0, a1
56+
; CHECK-NEXT: srliw a0, a0, 23
6157
; CHECK-NEXT: ret
6258
entry:
6359
%trunc = trunc nuw i64 %x to i16
@@ -69,7 +65,6 @@ entry:
6965
define ptr @gep_nusw_zext_nneg_add_trunc_nuw_nsw(ptr %p, i64 %x) nounwind {
7066
; CHECK-LABEL: gep_nusw_zext_nneg_add_trunc_nuw_nsw:
7167
; CHECK: # %bb.0: # %entry
72-
; CHECK-NEXT: sext.w a1, a1
7368
; CHECK-NEXT: slli a1, a1, 2
7469
; CHECK-NEXT: add a0, a1, a0
7570
; CHECK-NEXT: addi a0, a0, 20

‎llvm/test/CodeGen/X86/trunc-nsw-nuw.ll

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,10 @@ define zeroext i32 @trunc_nuw_nsw_urem(i64 %x) nounwind {
55
; CHECK-LABEL: trunc_nuw_nsw_urem:
66
; CHECK: # %bb.0: # %entry
77
; CHECK-NEXT: movq %rdi, %rax
8-
; CHECK-NEXT: movl %eax, %ecx
9-
; CHECK-NEXT: movl $3518437209, %edx # imm = 0xD1B71759
10-
; CHECK-NEXT: imulq %rcx, %rdx
11-
; CHECK-NEXT: shrq $45, %rdx
12-
; CHECK-NEXT: imull $10000, %edx, %ecx # imm = 0x2710
8+
; CHECK-NEXT: movl $3518437209, %ecx # imm = 0xD1B71759
9+
; CHECK-NEXT: imulq %rdi, %rcx
10+
; CHECK-NEXT: shrq $45, %rcx
11+
; CHECK-NEXT: imull $10000, %ecx, %ecx # imm = 0x2710
1312
; CHECK-NEXT: subl %ecx, %eax
1413
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
1514
; CHECK-NEXT: retq
@@ -22,8 +21,7 @@ entry:
2221
define i64 @zext_nneg_udiv_trunc_nuw(i64 %x) nounwind {
2322
; CHECK-LABEL: zext_nneg_udiv_trunc_nuw:
2423
; CHECK: # %bb.0: # %entry
25-
; CHECK-NEXT: movzwl %di, %eax
26-
; CHECK-NEXT: imull $52429, %eax, %eax # imm = 0xCCCD
24+
; CHECK-NEXT: imull $52429, %edi, %eax # imm = 0xCCCD
2725
; CHECK-NEXT: shrl $23, %eax
2826
; CHECK-NEXT: retq
2927
entry:
@@ -36,8 +34,7 @@ entry:
3634
define i64 @sext_udiv_trunc_nuw(i64 %x) nounwind {
3735
; CHECK-LABEL: sext_udiv_trunc_nuw:
3836
; CHECK: # %bb.0: # %entry
39-
; CHECK-NEXT: movzwl %di, %eax
40-
; CHECK-NEXT: imull $52429, %eax, %eax # imm = 0xCCCD
37+
; CHECK-NEXT: imull $52429, %edi, %eax # imm = 0xCCCD
4138
; CHECK-NEXT: shrl $23, %eax
4239
; CHECK-NEXT: retq
4340
entry:
@@ -50,8 +47,7 @@ entry:
5047
define ptr @gep_nusw_zext_nneg_add_trunc_nuw_nsw(ptr %p, i64 %x) nounwind {
5148
; CHECK-LABEL: gep_nusw_zext_nneg_add_trunc_nuw_nsw:
5249
; CHECK: # %bb.0: # %entry
53-
; CHECK-NEXT: movl %esi, %eax
54-
; CHECK-NEXT: leaq 20(%rdi,%rax,4), %rax
50+
; CHECK-NEXT: leaq 20(%rdi,%rsi,4), %rax
5551
; CHECK-NEXT: retq
5652
entry:
5753
%trunc = trunc nuw nsw i64 %x to i32

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