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Thorsten Schütt
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14 files changed

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14 files changed

+147
-153
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‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,7 @@ def binop_right_undef_to_undef: GICombineRule<
420420

421421
def unary_undef_to_zero: GICombineRule<
422422
(defs root:$root),
423-
(match (wip_match_opcode G_ABS):$root,
423+
(match (wip_match_opcode G_ABS, G_ZEXT):$root,
424424
[{ return Helper.matchOperandIsUndef(*${root}, 1); }]),
425425
(apply [{ Helper.replaceInstWithConstant(*${root}, 0); }])>;
426426

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2944,8 +2944,11 @@ void CombinerHelper::replaceInstWithFConstant(MachineInstr &MI, double C) {
29442944

29452945
void CombinerHelper::replaceInstWithConstant(MachineInstr &MI, int64_t C) {
29462946
assert(MI.getNumDefs() == 1 && "Expected only one def?");
2947-
Builder.buildConstant(MI.getOperand(0), C);
2948-
MI.eraseFromParent();
2947+
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2948+
if (isLegalOrBeforeLegalizer({TargetOpcode::G_CONSTANT, {DstTy}})) {
2949+
Builder.buildConstant(MI.getOperand(0), C);
2950+
MI.eraseFromParent();
2951+
}
29492952
}
29502953

29512954
void CombinerHelper::replaceInstWithConstant(MachineInstr &MI, APInt C) {

‎llvm/lib/CodeGen/GlobalISel/CombinerHelperArtifacts.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,14 +45,14 @@ bool CombinerHelper::matchMergeXAndUndef(const MachineInstr &MI,
4545
//
4646
// ->
4747
//
48-
// %0:_(s16) = G_ANYEXT %bits_0_7:(s8)
48+
// %0:_(s16) = G_ZEXT %bits_0_7:(s8)
4949
//
5050

51-
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ANYEXT, {DstTy, SrcTy}}))
51+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ZEXT, {DstTy, SrcTy}}))
5252
return false;
5353

5454
MatchInfo = [=](MachineIRBuilder &B) {
55-
B.buildAnyExt(Dst, Merge->getSourceReg(0));
55+
B.buildZExt(Dst, Merge->getSourceReg(0));
5656
};
5757
return true;
5858
}

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir

Lines changed: 15 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@ name: test_combine_unmerge_merge
99
body: |
1010
bb.1:
1111
; CHECK-LABEL: name: test_combine_unmerge_merge
12-
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
13-
; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
14-
; CHECK-NEXT: $w1 = COPY [[DEF]](s32)
12+
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
13+
; CHECK-NEXT: $w0 = COPY [[C]](s32)
14+
; CHECK-NEXT: $w1 = COPY [[C]](s32)
1515
%0:_(s32) = G_IMPLICIT_DEF
1616
%1:_(s32) = G_IMPLICIT_DEF
1717
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -113,9 +113,11 @@ name: test_combine_unmerge_bitcast_merge
113113
body: |
114114
bb.1:
115115
; CHECK-LABEL: name: test_combine_unmerge_bitcast_merge
116-
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
117-
; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
118-
; CHECK-NEXT: $w1 = COPY [[DEF]](s32)
116+
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
117+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[C]](s64)
118+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BITCAST]](<2 x s32>)
119+
; CHECK-NEXT: $w0 = COPY [[UV]](s32)
120+
; CHECK-NEXT: $w1 = COPY [[UV1]](s32)
119121
%0:_(s32) = G_IMPLICIT_DEF
120122
%1:_(s32) = G_IMPLICIT_DEF
121123
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -133,11 +135,11 @@ name: test_combine_unmerge_merge_incompatible_types
133135
body: |
134136
bb.1:
135137
; CHECK-LABEL: name: test_combine_unmerge_merge_incompatible_types
136-
; CHECK: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
137-
; CHECK-NEXT: $h0 = COPY [[DEF]](s16)
138-
; CHECK-NEXT: $h1 = COPY [[DEF]](s16)
139-
; CHECK-NEXT: $h2 = COPY [[DEF]](s16)
140-
; CHECK-NEXT: $h3 = COPY [[DEF]](s16)
138+
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
139+
; CHECK-NEXT: $h0 = COPY [[C]](s16)
140+
; CHECK-NEXT: $h1 = COPY [[C]](s16)
141+
; CHECK-NEXT: $h2 = COPY [[C]](s16)
142+
; CHECK-NEXT: $h3 = COPY [[C]](s16)
141143
%0:_(s32) = G_IMPLICIT_DEF
142144
%1:_(s32) = G_IMPLICIT_DEF
143145
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
@@ -542,7 +544,7 @@ body: |
542544
bb.1:
543545
; CHECK-LABEL: name: test_merge_undef
544546
; CHECK: %opaque:_(s64) = COPY $x0
545-
; CHECK-NEXT: %me:_(s128) = G_ANYEXT %opaque(s64)
547+
; CHECK-NEXT: %me:_(s128) = G_ZEXT %opaque(s64)
546548
; CHECK-NEXT: $q0 = COPY %me(s128)
547549
%opaque:_(s64) = COPY $x0
548550
%def:_(s64) = G_IMPLICIT_DEF
@@ -558,7 +560,7 @@ body: |
558560
; CHECK-LABEL: name: test_merge_undef_multi_use
559561
; CHECK: %opaque:_(s64) = COPY $x0
560562
; CHECK-NEXT: %def:_(s64) = G_IMPLICIT_DEF
561-
; CHECK-NEXT: %me:_(s128) = G_ANYEXT %opaque(s64)
563+
; CHECK-NEXT: %me:_(s128) = G_ZEXT %opaque(s64)
562564
; CHECK-NEXT: $q0 = COPY %me(s128)
563565
; CHECK-NEXT: $x0 = COPY %def(s64)
564566
%opaque:_(s64) = COPY $x0

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -322,17 +322,18 @@ define void @typei1_orig(i64 %a, ptr %p, ptr %q) {
322322
;
323323
; CHECK-GI-LABEL: typei1_orig:
324324
; CHECK-GI: // %bb.0:
325-
; CHECK-GI-NEXT: ldr q1, [x2]
325+
; CHECK-GI-NEXT: ldr q0, [x2]
326326
; CHECK-GI-NEXT: cmp x0, #0
327-
; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
328327
; CHECK-GI-NEXT: cset w8, gt
329-
; CHECK-GI-NEXT: neg v1.8h, v1.8h
330-
; CHECK-GI-NEXT: dup v2.8h, w8
328+
; CHECK-GI-NEXT: neg v0.8h, v0.8h
329+
; CHECK-GI-NEXT: dup v1.8h, w8
330+
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
331+
; CHECK-GI-NEXT: mul v1.8h, v0.8h, v1.8h
332+
; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, #0
331333
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
332-
; CHECK-GI-NEXT: mul v1.8h, v1.8h, v2.8h
333334
; CHECK-GI-NEXT: cmeq v1.8h, v1.8h, #0
334335
; CHECK-GI-NEXT: mvn v1.16b, v1.16b
335-
; CHECK-GI-NEXT: uzp1 v0.16b, v1.16b, v0.16b
336+
; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b
336337
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
337338
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
338339
; CHECK-GI-NEXT: str q0, [x1]

‎llvm/test/CodeGen/AArch64/bswap.ll

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -45,24 +45,14 @@ define i64 @bswap_i16_to_i64_anyext(i16 %a) {
4545

4646
; The zext here is optimised to an any_extend during isel..
4747
define i128 @bswap_i16_to_i128_anyext(i16 %a) {
48-
; CHECK-SD-LABEL: bswap_i16_to_i128_anyext:
49-
; CHECK-SD: // %bb.0:
50-
; CHECK-SD-NEXT: mov w8, w0
51-
; CHECK-SD-NEXT: mov x0, xzr
52-
; CHECK-SD-NEXT: rev w8, w8
53-
; CHECK-SD-NEXT: lsr w8, w8, #16
54-
; CHECK-SD-NEXT: lsl x1, x8, #48
55-
; CHECK-SD-NEXT: ret
56-
;
57-
; CHECK-GI-LABEL: bswap_i16_to_i128_anyext:
58-
; CHECK-GI: // %bb.0:
59-
; CHECK-GI-NEXT: mov w8, w0
60-
; CHECK-GI-NEXT: mov x0, xzr
61-
; CHECK-GI-NEXT: rev w8, w8
62-
; CHECK-GI-NEXT: lsr w8, w8, #16
63-
; CHECK-GI-NEXT: and x8, x8, #0xffff
64-
; CHECK-GI-NEXT: lsl x1, x8, #48
65-
; CHECK-GI-NEXT: ret
48+
; CHECK-LABEL: bswap_i16_to_i128_anyext:
49+
; CHECK: // %bb.0:
50+
; CHECK-NEXT: mov w8, w0
51+
; CHECK-NEXT: mov x0, xzr
52+
; CHECK-NEXT: rev w8, w8
53+
; CHECK-NEXT: lsr w8, w8, #16
54+
; CHECK-NEXT: lsl x1, x8, #48
55+
; CHECK-NEXT: ret
6656
%3 = call i16 @llvm.bswap.i16(i16 %a)
6757
%4 = zext i16 %3 to i128
6858
%5 = shl i128 %4, 112

‎llvm/test/CodeGen/AArch64/extract-vector-elt.ll

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -8,17 +8,10 @@
88
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract_const
99

1010
define i64 @extract_v2i64_undef_index(<2 x i64> %a, i32 %c) {
11-
; CHECK-SD-LABEL: extract_v2i64_undef_index:
12-
; CHECK-SD: // %bb.0: // %entry
13-
; CHECK-SD-NEXT: fmov x0, d0
14-
; CHECK-SD-NEXT: ret
15-
;
16-
; CHECK-GI-LABEL: extract_v2i64_undef_index:
17-
; CHECK-GI: // %bb.0: // %entry
18-
; CHECK-GI-NEXT: str q0, [sp, #-16]!
19-
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
20-
; CHECK-GI-NEXT: ldr x0, [sp], #16
21-
; CHECK-GI-NEXT: ret
11+
; CHECK-LABEL: extract_v2i64_undef_index:
12+
; CHECK: // %bb.0: // %entry
13+
; CHECK-NEXT: fmov x0, d0
14+
; CHECK-NEXT: ret
2215
entry:
2316
%d = extractelement <2 x i64> %a, i32 undef
2417
ret i64 %d

‎llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1884,22 +1884,22 @@ define amdgpu_ps i65 @s_ashr_i65(i65 inreg %value, i65 inreg %amount) {
18841884
define amdgpu_ps i65 @s_ashr_i65_33(i65 inreg %value) {
18851885
; GCN-LABEL: s_ashr_i65_33:
18861886
; GCN: ; %bb.0:
1887-
; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1888-
; GCN-NEXT: s_lshr_b32 s0, s1, 1
1889-
; GCN-NEXT: s_mov_b32 s1, 0
1890-
; GCN-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1891-
; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1892-
; GCN-NEXT: s_ashr_i32 s2, s3, 1
1887+
; GCN-NEXT: s_mov_b32 s3, 0
1888+
; GCN-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
1889+
; GCN-NEXT: s_lshr_b32 s2, s1, 1
1890+
; GCN-NEXT: s_lshl_b64 s[0:1], s[4:5], 31
1891+
; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
1892+
; GCN-NEXT: s_ashr_i32 s2, s5, 1
18931893
; GCN-NEXT: ; return to shader part epilog
18941894
;
18951895
; GFX10PLUS-LABEL: s_ashr_i65_33:
18961896
; GFX10PLUS: ; %bb.0:
1897-
; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x10000
1898-
; GFX10PLUS-NEXT: s_lshr_b32 s0, s1, 1
1899-
; GFX10PLUS-NEXT: s_mov_b32 s1, 0
1900-
; GFX10PLUS-NEXT: s_lshl_b64 s[4:5], s[2:3], 31
1901-
; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 1
1902-
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
1897+
; GFX10PLUS-NEXT: s_mov_b32 s3, 0
1898+
; GFX10PLUS-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x10000
1899+
; GFX10PLUS-NEXT: s_lshr_b32 s2, s1, 1
1900+
; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[4:5], 31
1901+
; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
1902+
; GFX10PLUS-NEXT: s_ashr_i32 s2, s5, 1
19031903
; GFX10PLUS-NEXT: ; return to shader part epilog
19041904
%result = ashr i65 %value, 33
19051905
ret i65 %result

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -261,8 +261,7 @@ body: |
261261
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_16
262262
; CHECK: liveins: $vgpr0
263263
; CHECK-NEXT: {{ $}}
264-
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
265-
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
264+
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
266265
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
267266
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
268267
%arg:_(s32) = COPY $vgpr0
@@ -284,8 +283,7 @@ body: |
284283
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_24
285284
; CHECK: liveins: $vgpr0
286285
; CHECK-NEXT: {{ $}}
287-
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
288-
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
286+
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
289287
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
290288
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
291289
%arg:_(s32) = COPY $vgpr0

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