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[WebAssembly] Implement all f16x8 unary instructions. (#94063)
All of these instructions can be generated using regular LL intrinsics. Specified at: https://github.com/WebAssembly/half-precision/blob/29a9b9462c9285d4ccc1a5dc39214ddfd1892658/proposals/half-precision/Overview.md
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -828,12 +828,18 @@ multiclass SIMDBitwise<SDPatternOperator node, string name, bits<32> simdop,
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(!cast<NI>(NAME) $lhs, $rhs)>;
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}
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multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
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multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name,
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bits<32> simdop, list<Predicate> reqs = []> {
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defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
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[(set (vec.vt V128:$dst),
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(vec.vt (node (vec.vt V128:$v))))],
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vec.prefix#"."#name#"\t$dst, $v",
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vec.prefix#"."#name, simdop>;
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vec.prefix#"."#name, simdop, reqs>;
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}
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multiclass HalfPrecisionUnary<Vec vec, SDPatternOperator node, string name,
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bits<32> simdop> {
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defm "" : SIMDUnary<vec, node, name, simdop, [HasHalfPrecision]>;
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}
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// Bitwise logic: v128.not
@@ -1190,6 +1196,10 @@ defm EXTMUL_HIGH_U :
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multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
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defm "" : SIMDUnary<F32x4, node, name, baseInst>;
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defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>;
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// Unlike F32x4 and F64x2 there's not a gap in the opcodes between "neg" and
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// "sqrt" so subtract one from the offset.
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defm "" : HalfPrecisionUnary<F16x8, node, name,
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!add(baseInst,!if(!eq(name, "sqrt"), 80, 81))>;
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}
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// Absolute value: abs
@@ -1210,14 +1220,20 @@ defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>;
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defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>;
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defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>;
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defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>;
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defm CEIL : HalfPrecisionUnary<F16x8, fceil, "ceil", 0x13c>;
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defm FLOOR : HalfPrecisionUnary<F16x8, ffloor, "floor", 0x13d>;
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defm TRUNC : HalfPrecisionUnary<F16x8, ftrunc, "trunc", 0x13e>;
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defm NEAREST : HalfPrecisionUnary<F16x8, fnearbyint, "nearest", 0x13f>;
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// WebAssembly doesn't expose inexact exceptions, so map frint to fnearbyint.
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def : Pat<(v4f32 (frint (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>;
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def : Pat<(v2f64 (frint (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>;
1231+
def : Pat<(v8f16 (frint (v8f16 V128:$src))), (NEAREST_F16x8 V128:$src)>;
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// WebAssembly always rounds ties-to-even, so map froundeven to fnearbyint.
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def : Pat<(v4f32 (froundeven (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>;
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def : Pat<(v2f64 (froundeven (v2f64 V128:$src))), (NEAREST_F64x2 V128:$src)>;
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def : Pat<(v8f16 (froundeven (v8f16 V128:$src))), (NEAREST_F16x8 V128:$src)>;
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//===----------------------------------------------------------------------===//
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// Floating-point binary arithmetic

‎llvm/test/CodeGen/WebAssembly/half-precision.ll

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,3 +157,92 @@ define <8 x i1> @compare_oge_v8f16 (<8 x half> %x, <8 x half> %y) {
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%res = fcmp oge <8 x half> %x, %y
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ret <8 x i1> %res
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}
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; CHECK-LABEL: abs_v8f16:
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; CHECK-NEXT: .functype abs_v8f16 (v128) -> (v128)
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; CHECK-NEXT: f16x8.abs $push0=, $0
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; CHECK-NEXT: return $pop0
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>) nounwind readnone
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define <8 x half> @abs_v8f16(<8 x half> %x) {
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%a = call <8 x half> @llvm.fabs.v8f16(<8 x half> %x)
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ret <8 x half> %a
169+
}
170+
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; CHECK-LABEL: neg_v8f16:
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; CHECK-NEXT: .functype neg_v8f16 (v128) -> (v128)
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; CHECK-NEXT: f16x8.neg $push0=, $0
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; CHECK-NEXT: return $pop0
175+
define <8 x half> @neg_v8f16(<8 x half> %x) {
176+
%a = fsub nsz <8 x half> <half 0., half 0., half 0., half 0., half 0., half 0., half 0., half 0.>, %x
177+
ret <8 x half> %a
178+
}
179+
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; CHECK-LABEL: sqrt_v8f16:
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; CHECK-NEXT: .functype sqrt_v8f16 (v128) -> (v128)
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; CHECK-NEXT: f16x8.sqrt $push0=, $0
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; CHECK-NEXT: return $pop0
184+
declare <8 x half> @llvm.sqrt.v8f16(<8 x half> %x)
185+
define <8 x half> @sqrt_v8f16(<8 x half> %x) {
186+
%a = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %x)
187+
ret <8 x half> %a
188+
}
189+
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; CHECK-LABEL: ceil_v8f16:
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; CHECK-NEXT: .functype ceil_v8f16 (v128) -> (v128){{$}}
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; CHECK-NEXT: f16x8.ceil $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
195+
define <8 x half> @ceil_v8f16(<8 x half> %a) {
196+
%v = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)
197+
ret <8 x half> %v
198+
}
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; CHECK-LABEL: floor_v8f16:
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; CHECK-NEXT: .functype floor_v8f16 (v128) -> (v128){{$}}
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; CHECK-NEXT: f16x8.floor $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
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declare <8 x half> @llvm.floor.v8f16(<8 x half>)
205+
define <8 x half> @floor_v8f16(<8 x half> %a) {
206+
%v = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)
207+
ret <8 x half> %v
208+
}
209+
210+
; CHECK-LABEL: trunc_v8f16:
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; CHECK-NEXT: .functype trunc_v8f16 (v128) -> (v128){{$}}
212+
; CHECK-NEXT: f16x8.trunc $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
214+
declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
215+
define <8 x half> @trunc_v8f16(<8 x half> %a) {
216+
%v = call <8 x half> @llvm.trunc.v8f16(<8 x half> %a)
217+
ret <8 x half> %v
218+
}
219+
220+
; CHECK-LABEL: nearest_v8f16:
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; CHECK-NEXT: .functype nearest_v8f16 (v128) -> (v128){{$}}
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; CHECK-NEXT: f16x8.nearest $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
224+
declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)
225+
define <8 x half> @nearest_v8f16(<8 x half> %a) {
226+
%v = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %a)
227+
ret <8 x half> %v
228+
}
229+
230+
; CHECK-LABEL: nearest_v8f16_via_rint:
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; CHECK-NEXT: .functype nearest_v8f16_via_rint (v128) -> (v128){{$}}
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; CHECK-NEXT: f16x8.nearest $push[[R:[0-9]+]]=, $0{{$}}
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; CHECK-NEXT: return $pop[[R]]{{$}}
234+
declare <8 x half> @llvm.rint.v8f16(<8 x half>)
235+
define <8 x half> @nearest_v8f16_via_rint(<8 x half> %a) {
236+
%v = call <8 x half> @llvm.rint.v8f16(<8 x half> %a)
237+
ret <8 x half> %v
238+
}
239+
240+
; CHECK-LABEL: nearest_v8f16_via_roundeven:
241+
; CHECK-NEXT: .functype nearest_v8f16_via_roundeven (v128) -> (v128){{$}}
242+
; CHECK-NEXT: f16x8.nearest $push[[R:[0-9]+]]=, $0{{$}}
243+
; CHECK-NEXT: return $pop[[R]]{{$}}
244+
declare <8 x half> @llvm.roundeven.v8f16(<8 x half>)
245+
define <8 x half> @nearest_v8f16_via_roundeven(<8 x half> %a) {
246+
%v = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %a)
247+
ret <8 x half> %v
248+
}

‎llvm/test/MC/WebAssembly/simd-encodings.s

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -893,4 +893,25 @@ main:
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# CHECK: f16x8.ge # encoding: [0xfd,0xc5,0x02]
894894
f16x8.ge
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896+
# CHECK: f16x8.abs # encoding: [0xfd,0xb1,0x02]
897+
f16x8.abs
898+
899+
# CHECK: f16x8.neg # encoding: [0xfd,0xb2,0x02]
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f16x8.neg
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902+
# CHECK: f16x8.sqrt # encoding: [0xfd,0xb3,0x02]
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f16x8.sqrt
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# CHECK: f16x8.ceil # encoding: [0xfd,0xbc,0x02]
906+
f16x8.ceil
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# CHECK: f16x8.floor # encoding: [0xfd,0xbd,0x02]
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f16x8.floor
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# CHECK: f16x8.trunc # encoding: [0xfd,0xbe,0x02]
912+
f16x8.trunc
913+
914+
# CHECK: f16x8.nearest # encoding: [0xfd,0xbf,0x02]
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f16x8.nearest
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896917
end_function

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