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[mlir][ArmSME] Move ArmSME -> intrinsics lowerings to convert-arm-sme-to-llvm pass (#72890)
This gives more flexibility with when these lowerings are performed, without also lowering unrelated vector ops. This is a NFC (other than adding a new `-convert-arm-sme-to-llvm` pass)
1 parent 55f067f commit dff97c1

26 files changed

+190
-122
lines changed

‎mlir/include/mlir/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.h

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@@ -0,0 +1,38 @@
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//===- ArmSMEToLLVM.h - Convert ArmSME to LLVM dialect ----------*- C++ -*-===//
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//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
7+
//===----------------------------------------------------------------------===//
8+
9+
#ifndef MLIR_CONVERSION_ARMSMETOLLVM_ARMSMETOLLVM_H_
10+
#define MLIR_CONVERSION_ARMSMETOLLVM_ARMSMETOLLVM_H_
11+
12+
#include <memory>
13+
14+
#include "mlir/Dialect/ArmSME/Transforms/Passes.h"
15+
16+
namespace mlir {
17+
class Pass;
18+
class RewritePatternSet;
19+
20+
#define GEN_PASS_DECL_CONVERTARMSMETOLLVM
21+
#include "mlir/Conversion/Passes.h.inc"
22+
23+
using arm_sme::ArmSMETypeConverter;
24+
25+
/// Create a pass to convert from the ArmSME dialect to LLVM intrinsics.
26+
std::unique_ptr<Pass> createConvertArmSMEToLLVMPass();
27+
28+
/// Configure target to convert from the ArmSME dialect to LLVM intrinsics.
29+
void configureArmSMEToLLVMConversionLegality(ConversionTarget &target);
30+
31+
/// Populate the given list with patterns that convert from the ArmSME dialect
32+
/// to LLVM intrinsics.
33+
void populateArmSMEToLLVMConversionPatterns(ArmSMETypeConverter &converter,
34+
RewritePatternSet &patterns);
35+
36+
} // namespace mlir
37+
38+
#endif // MLIR_CONVERSION_ARMSMETOLLVM_ARMSMETOLLVM_H_

‎mlir/include/mlir/Conversion/Passes.h

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@@ -15,6 +15,7 @@
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#include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h"
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#include "mlir/Conversion/ArithToSPIRV/ArithToSPIRV.h"
1717
#include "mlir/Conversion/ArmNeon2dToIntr/ArmNeon2dToIntr.h"
18+
#include "mlir/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.h"
1819
#include "mlir/Conversion/ArmSMEToSCF/ArmSMEToSCF.h"
1920
#include "mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h"
2021
#include "mlir/Conversion/BufferizationToMemRef/BufferizationToMemRef.h"

‎mlir/include/mlir/Conversion/Passes.td

Lines changed: 14 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1241,6 +1241,20 @@ def ConvertArmSMEToSCF : Pass<"convert-arm-sme-to-scf"> {
12411241
];
12421242
}
12431243

1244+
//===----------------------------------------------------------------------===//
1245+
// ArmSMEToLLVM
1246+
//===----------------------------------------------------------------------===//
1247+
1248+
def ConvertArmSMEToLLVM : Pass<"convert-arm-sme-to-llvm"> {
1249+
let summary = "Lower the operations from the ArmSME dialect into the LLVM "
1250+
"dialect";
1251+
let constructor = "mlir::createConvertArmSMEToLLVMPass()";
1252+
let dependentDialects = [
1253+
"arm_sme::ArmSMEDialect",
1254+
"LLVM::LLVMDialect"
1255+
];
1256+
}
1257+
12441258
//===----------------------------------------------------------------------===//
12451259
// VectorToLLVM
12461260
//===----------------------------------------------------------------------===//
@@ -1280,10 +1294,6 @@ def ConvertVectorToLLVMPass : Pass<"convert-vector-to-llvm"> {
12801294
"bool", /*default=*/"false",
12811295
"Enables the use of ArmSVE dialect while lowering the vector "
12821296
"dialect.">,
1283-
Option<"armSME", "enable-arm-sme",
1284-
"bool", /*default=*/"false",
1285-
"Enables the use of ArmSME dialect while lowering the vector "
1286-
"dialect.">,
12871297
Option<"x86Vector", "enable-x86vector",
12881298
"bool", /*default=*/"false",
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"Enables the use of X86Vector dialect while lowering the vector "

‎mlir/include/mlir/Dialect/ArmSME/Transforms/Transforms.h

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Original file line numberDiff line numberDiff line change
@@ -20,15 +20,6 @@ void populateVectorTransferLoweringPatterns(LLVMTypeConverter &converter,
2020
RewritePatternSet &patterns);
2121
} // namespace arm_sme
2222

23-
/// Collect a set of patterns to lower ArmSME ops to ops that map to LLVM
24-
/// intrinsics.
25-
void populateArmSMELegalizeForLLVMExportPatterns(LLVMTypeConverter &converter,
26-
RewritePatternSet &patterns);
27-
28-
/// Configure the target to support lowering ArmSME ops to ops that map to LLVM
29-
/// intrinsics.
30-
void configureArmSMELegalizeForExportTarget(LLVMConversionTarget &target);
31-
3223
} // namespace mlir
3324

3425
#endif // MLIR_DIALECT_ARMSME_TRANSFORMS_H

‎mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp renamed to ‎mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp

Lines changed: 73 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -1,24 +1,34 @@
1-
//===- LegalizeForLLVMExport.cpp - Prepare ArmSME for LLVM translation ----===//
1+
//===- ArmSMEToLLVM.cpp - Convert ArmSME to LLVM dialect ------------------===//
22
//
33
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
44
// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements lowering of ArmSME operations to LLVM intrinsics.
10+
//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.h"
814

915
#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
1016
#include "mlir/Conversion/LLVMCommon/Pattern.h"
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#include "mlir/Dialect/Arith/IR/Arith.h"
1218
#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
13-
#include "mlir/Dialect/ArmSME/Transforms/Transforms.h"
1419
#include "mlir/Dialect/ArmSME/Utils/Utils.h"
1520
#include "mlir/Dialect/Func/IR/FuncOps.h"
1621
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
17-
#include "mlir/Dialect/SCF/IR/SCF.h"
1822
#include "mlir/Dialect/Vector/IR/VectorOps.h"
23+
#include "mlir/Pass/Pass.h"
24+
#include "mlir/Transforms/DialectConversion.h"
25+
26+
namespace mlir {
27+
#define GEN_PASS_DEF_CONVERTARMSMETOLLVM
28+
#include "mlir/Conversion/Passes.h.inc"
29+
} // namespace mlir
1930

2031
using namespace mlir;
21-
using namespace mlir::arm_sme;
2232

2333
namespace {
2434

@@ -40,11 +50,11 @@ namespace {
4050
/// The 'arm_sme.cast_tile_to_vector' (which models the return) and the
4151
/// 'arith.shli' (which generates the mask) will be folded away after tile
4252
/// allocation and canonization.
43-
struct ZeroOpConversion : public ConvertOpToLLVMPattern<ZeroOp> {
44-
using ConvertOpToLLVMPattern<ZeroOp>::ConvertOpToLLVMPattern;
53+
struct ZeroOpConversion : public ConvertOpToLLVMPattern<arm_sme::ZeroOp> {
54+
using ConvertOpToLLVMPattern<arm_sme::ZeroOp>::ConvertOpToLLVMPattern;
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4656
LogicalResult
47-
matchAndRewrite(ZeroOp zero, OpAdaptor adaptor,
57+
matchAndRewrite(arm_sme::ZeroOp zero, OpAdaptor adaptor,
4858
ConversionPatternRewriter &rewriter) const override {
4959
auto loc = zero.getLoc();
5060

@@ -121,7 +131,7 @@ struct ZeroOpConversion : public ConvertOpToLLVMPattern<ZeroOp> {
121131
};
122132

123133
/// Lower `arm_sme.load_tile_slice` to SME intrinsics.
124-
struct LoadTileSliceToArmSMELowering
134+
struct LoadTileSliceConversion
125135
: public ConvertOpToLLVMPattern<arm_sme::LoadTileSliceOp> {
126136
using ConvertOpToLLVMPattern<
127137
arm_sme::LoadTileSliceOp>::ConvertOpToLLVMPattern;
@@ -220,7 +230,7 @@ struct LoadTileSliceToArmSMELowering
220230
};
221231

222232
/// Lower for `arm_sme.store_tile_slice` to SME intrinsics.
223-
struct StoreTileSliceToArmSMELowering
233+
struct StoreTileSliceConversion
224234
: public ConvertOpToLLVMPattern<arm_sme::StoreTileSliceOp> {
225235
using ConvertOpToLLVMPattern<
226236
arm_sme::StoreTileSliceOp>::ConvertOpToLLVMPattern;
@@ -313,7 +323,7 @@ struct StoreTileSliceToArmSMELowering
313323
};
314324

315325
/// Lower `arm_sme.move_vector_to_tile_slice` to SME intrinsics.
316-
struct MoveVectorToTileSliceToArmSMELowering
326+
struct MoveVectorToTileSliceConversion
317327
: public ConvertOpToLLVMPattern<arm_sme::MoveVectorToTileSliceOp> {
318328
using ConvertOpToLLVMPattern<
319329
arm_sme::MoveVectorToTileSliceOp>::ConvertOpToLLVMPattern;
@@ -373,7 +383,7 @@ struct MoveVectorToTileSliceToArmSMELowering
373383
};
374384

375385
/// Lower `arm_sme.move_tile_slice_to_vector` to SME intrinsics.
376-
struct MoveTileSliceToVectorArmSMELowering
386+
struct MoveTileSliceToVectorConversion
377387
: public ConvertOpToLLVMPattern<arm_sme::MoveTileSliceToVectorOp> {
378388
using ConvertOpToLLVMPattern<
379389
arm_sme::MoveTileSliceToVectorOp>::ConvertOpToLLVMPattern;
@@ -456,7 +466,8 @@ struct OuterProductOpConversion
456466
// * half-precision - +sme2p1,+b16b16
457467
//
458468
// It should be possible to control lowering based on target features.
459-
// [1] https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
469+
// [1]
470+
// https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
460471
if ((vectorType.getRank() != 2) || !vectorType.allDimsScalable())
461472
return false;
462473

@@ -475,7 +486,7 @@ struct OuterProductOpConversion
475486
};
476487

477488
// TODO: Support CombiningKind::Sub for outer products.
478-
if (outerProductOp.getKind() != CombiningKind::Add)
489+
if (outerProductOp.getKind() != arm_sme::CombiningKind::Add)
479490
return outerProductOp.emitError("unsupported kind");
480491

481492
auto resultVectorType = outerProductOp.getResultType();
@@ -522,32 +533,56 @@ struct OuterProductOpConversion
522533

523534
} // namespace
524535

525-
void mlir::configureArmSMELegalizeForExportTarget(
526-
LLVMConversionTarget &target) {
536+
namespace {
537+
538+
struct ConvertArmSMEToLLVMPass
539+
: public impl::ConvertArmSMEToLLVMBase<ConvertArmSMEToLLVMPass> {
540+
void runOnOperation() override {
541+
LLVMConversionTarget target(getContext());
542+
RewritePatternSet patterns(&getContext());
543+
ArmSMETypeConverter converter(&getContext(),
544+
LowerToLLVMOptions(&getContext()));
545+
546+
configureArmSMEToLLVMConversionLegality(target);
547+
populateArmSMEToLLVMConversionPatterns(converter, patterns);
548+
549+
if (failed(applyPartialConversion(getOperation(), target,
550+
std::move(patterns))))
551+
signalPassFailure();
552+
}
553+
};
554+
555+
} // namespace
556+
557+
void mlir::configureArmSMEToLLVMConversionLegality(ConversionTarget &target) {
558+
target.addIllegalDialect<arm_sme::ArmSMEDialect>();
527559
target.addLegalOp<
528-
scf::ForOp, scf::YieldOp, arm_sme::CastTileToVector,
529-
arm_sme::CastVectorToTile, arm_sme::aarch64_sme_zero,
530-
arm_sme::aarch64_sme_str, arm_sme::aarch64_sme_ld1b_horiz,
531-
arm_sme::aarch64_sme_ld1h_horiz, arm_sme::aarch64_sme_ld1w_horiz,
532-
arm_sme::aarch64_sme_ld1d_horiz, arm_sme::aarch64_sme_ld1q_horiz,
533-
arm_sme::aarch64_sme_st1b_horiz, arm_sme::aarch64_sme_st1h_horiz,
534-
arm_sme::aarch64_sme_st1w_horiz, arm_sme::aarch64_sme_st1d_horiz,
535-
arm_sme::aarch64_sme_st1q_horiz, arm_sme::aarch64_sme_ld1b_vert,
536-
arm_sme::aarch64_sme_ld1h_vert, arm_sme::aarch64_sme_ld1w_vert,
537-
arm_sme::aarch64_sme_ld1d_vert, arm_sme::aarch64_sme_ld1q_vert,
538-
arm_sme::aarch64_sme_st1b_vert, arm_sme::aarch64_sme_st1h_vert,
539-
arm_sme::aarch64_sme_st1w_vert, arm_sme::aarch64_sme_st1d_vert,
540-
arm_sme::aarch64_sme_st1q_vert, arm_sme::aarch64_sme_read_horiz,
541-
arm_sme::aarch64_sme_read_vert, arm_sme::aarch64_sme_write_horiz,
542-
arm_sme::aarch64_sme_write_vert, arm_sme::aarch64_sme_mopa>();
543-
target.addLegalOp<GetTileID>();
544-
target.addIllegalOp<vector::OuterProductOp>();
560+
arm_sme::GetTileID, arm_sme::CastTileToVector, arm_sme::CastVectorToTile,
561+
arm_sme::aarch64_sme_zero, arm_sme::aarch64_sme_str,
562+
arm_sme::aarch64_sme_ld1b_horiz, arm_sme::aarch64_sme_ld1h_horiz,
563+
arm_sme::aarch64_sme_ld1w_horiz, arm_sme::aarch64_sme_ld1d_horiz,
564+
arm_sme::aarch64_sme_ld1q_horiz, arm_sme::aarch64_sme_st1b_horiz,
565+
arm_sme::aarch64_sme_st1h_horiz, arm_sme::aarch64_sme_st1w_horiz,
566+
arm_sme::aarch64_sme_st1d_horiz, arm_sme::aarch64_sme_st1q_horiz,
567+
arm_sme::aarch64_sme_ld1b_vert, arm_sme::aarch64_sme_ld1h_vert,
568+
arm_sme::aarch64_sme_ld1w_vert, arm_sme::aarch64_sme_ld1d_vert,
569+
arm_sme::aarch64_sme_ld1q_vert, arm_sme::aarch64_sme_st1b_vert,
570+
arm_sme::aarch64_sme_st1h_vert, arm_sme::aarch64_sme_st1w_vert,
571+
arm_sme::aarch64_sme_st1d_vert, arm_sme::aarch64_sme_st1q_vert,
572+
arm_sme::aarch64_sme_read_horiz, arm_sme::aarch64_sme_read_vert,
573+
arm_sme::aarch64_sme_write_horiz, arm_sme::aarch64_sme_write_vert,
574+
arm_sme::aarch64_sme_mopa>();
575+
target.addLegalDialect<arith::ArithDialect>();
576+
target.addLegalOp<UnrealizedConversionCastOp>();
577+
}
578+
579+
void mlir::populateArmSMEToLLVMConversionPatterns(
580+
ArmSMETypeConverter &converter, RewritePatternSet &patterns) {
581+
patterns.add<LoadTileSliceConversion, MoveTileSliceToVectorConversion,
582+
MoveVectorToTileSliceConversion, StoreTileSliceConversion,
583+
OuterProductOpConversion, ZeroOpConversion>(converter);
545584
}
546585

547-
void mlir::populateArmSMELegalizeForLLVMExportPatterns(
548-
LLVMTypeConverter &converter, RewritePatternSet &patterns) {
549-
patterns.add<
550-
LoadTileSliceToArmSMELowering, MoveTileSliceToVectorArmSMELowering,
551-
MoveVectorToTileSliceToArmSMELowering, StoreTileSliceToArmSMELowering,
552-
OuterProductOpConversion, ZeroOpConversion>(converter);
586+
std::unique_ptr<Pass> mlir::createConvertArmSMEToLLVMPass() {
587+
return std::make_unique<ConvertArmSMEToLLVMPass>();
553588
}

‎mlir/lib/Conversion/ArmSMEToLLVM/CMakeLists.txt

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@@ -0,0 +1,16 @@
1+
add_mlir_conversion_library(MLIRArmSMEToLLVM
2+
ArmSMEToLLVM.cpp
3+
4+
ADDITIONAL_HEADER_DIRS
5+
${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/ArmSMEToLLVM
6+
7+
DEPENDS
8+
MLIRConversionPassIncGen
9+
10+
LINK_LIBS PUBLIC
11+
MLIRArmSMETransforms
12+
MLIRArmSMEDialect
13+
MLIRArmSMEUtils
14+
MLIRTransforms
15+
MLIRLLVMCommonConversion
16+
MLIRLLVMDialect)

‎mlir/lib/Conversion/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ add_subdirectory(ArithToLLVM)
66
add_subdirectory(ArithToSPIRV)
77
add_subdirectory(ArmNeon2dToIntr)
88
add_subdirectory(ArmSMEToSCF)
9+
add_subdirectory(ArmSMEToLLVM)
910
add_subdirectory(AsyncToLLVM)
1011
add_subdirectory(BufferizationToMemRef)
1112
add_subdirectory(ComplexToLibm)

‎mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,6 @@
1414
#include "mlir/Dialect/AMX/Transforms.h"
1515
#include "mlir/Dialect/Arith/IR/Arith.h"
1616
#include "mlir/Dialect/ArmNeon/ArmNeonDialect.h"
17-
#include "mlir/Dialect/ArmSME/IR/ArmSME.h"
18-
#include "mlir/Dialect/ArmSME/Transforms/Passes.h"
19-
#include "mlir/Dialect/ArmSME/Transforms/Transforms.h"
2017
#include "mlir/Dialect/ArmSVE/IR/ArmSVEDialect.h"
2118
#include "mlir/Dialect/ArmSVE/Transforms/Transforms.h"
2219
#include "mlir/Dialect/Func/IR/FuncOps.h"
@@ -52,8 +49,6 @@ struct LowerVectorToLLVMPass
5249
registry.insert<arm_neon::ArmNeonDialect>();
5350
if (armSVE)
5451
registry.insert<arm_sve::ArmSVEDialect>();
55-
if (armSME)
56-
registry.insert<arm_sme::ArmSMEDialect>();
5752
if (amx)
5853
registry.insert<amx::AMXDialect>();
5954
if (x86Vector)
@@ -96,7 +91,6 @@ void LowerVectorToLLVMPass::runOnOperation() {
9691
target.addLegalDialect<arith::ArithDialect>();
9792
target.addLegalDialect<memref::MemRefDialect>();
9893
target.addLegalOp<UnrealizedConversionCastOp>();
99-
arm_sme::ArmSMETypeConverter armSMEConverter(&getContext(), options);
10094

10195
if (armNeon) {
10296
// TODO: we may or may not want to include in-dialect lowering to
@@ -108,10 +102,6 @@ void LowerVectorToLLVMPass::runOnOperation() {
108102
configureArmSVELegalizeForExportTarget(target);
109103
populateArmSVELegalizeForLLVMExportPatterns(converter, patterns);
110104
}
111-
if (armSME) {
112-
configureArmSMELegalizeForExportTarget(target);
113-
populateArmSMELegalizeForLLVMExportPatterns(armSMEConverter, patterns);
114-
}
115105
if (amx) {
116106
configureAMXLegalizeForExportTarget(target);
117107
populateAMXLegalizeForLLVMExportPatterns(converter, patterns);

‎mlir/lib/Dialect/ArmSME/Transforms/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
add_mlir_dialect_library(MLIRArmSMETransforms
22
ArmSMETypeConverter.cpp
33
EnableArmStreaming.cpp
4-
LegalizeForLLVMExport.cpp
54
TileAllocation.cpp
65

76
ADDITIONAL_HEADER_DIRS

‎mlir/test/Dialect/ArmSME/arm-sme-to-llvm-casts.mlir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: mlir-opt %s -convert-arm-sme-to-scf -convert-vector-to-llvm="enable-arm-sme" -split-input-file | FileCheck %s
1+
// RUN: mlir-opt %s -convert-arm-sme-to-scf -convert-arm-sme-to-llvm -split-input-file | FileCheck %s
22

33
// This test verifies the temporary casts that are emitted when lowering to
44
// intrinsics to preserve data flow are correct. Canonicalization will remove

‎mlir/test/Dialect/ArmSME/arm-sme-to-llvm.mlir

Lines changed: 1 addition & 1 deletion
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@@ -1,4 +1,4 @@
1-
// RUN: mlir-opt %s -convert-vector-to-llvm="enable-arm-sme" -cse -canonicalize -split-input-file -verify-diagnostics | FileCheck %s
1+
// RUN: mlir-opt %s -convert-arm-sme-to-llvm -cse -canonicalize -split-input-file -verify-diagnostics | FileCheck %s
22

33
// Test conversion of ArmSME ops to LLVM intrinsics.
44

‎mlir/test/Dialect/ArmSME/enable-arm-za.mlir

Lines changed: 3 additions & 3 deletions
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@@ -1,6 +1,6 @@
1-
// RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za -convert-vector-to-llvm="enable-arm-sme" | FileCheck %s -check-prefix=ENABLE-ZA
2-
// RUN: mlir-opt %s -enable-arm-streaming -convert-vector-to-llvm="enable-arm-sme" | FileCheck %s -check-prefix=DISABLE-ZA
3-
// RUN: mlir-opt %s -convert-vector-to-llvm="enable-arm-sme" | FileCheck %s -check-prefix=NO-ARM-STREAMING
1+
// RUN: mlir-opt %s -enable-arm-streaming=za-mode=new-za -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=ENABLE-ZA
2+
// RUN: mlir-opt %s -enable-arm-streaming -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=DISABLE-ZA
3+
// RUN: mlir-opt %s -convert-arm-sme-to-llvm | FileCheck %s -check-prefix=NO-ARM-STREAMING
44

55
// CHECK-LABEL: @declaration
66
func.func private @declaration()

‎mlir/test/Dialect/ArmSME/tile-zero-masks.mlir

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// RUN: mlir-opt %s -convert-vector-to-llvm="enable-arm-sme" \
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// RUN: mlir-opt %s -convert-arm-sme-to-llvm \
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// RUN: -allocate-arm-sme-tiles -canonicalize \
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// RUN: -allow-unregistered-dialect \
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// RUN: | FileCheck %s

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