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[RISCV] Add late optimization pass for RISC-V to optimize branch instructions
This is an alternative to #117060, and is stacked on #131684. Marking @mikhailramalho as Co-Author here because I got the idea of a late peephole pass and the test case from #117060. I use a late pass because we introduce the optimizable branches so late in the pipeline. Co-authored-by: Mikhail R. Gadelha <[email protected]>
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8 files changed

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-14
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8 files changed

+107
-14
lines changed

llvm/lib/Target/RISCV/CMakeLists.txt

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@@ -35,6 +35,7 @@ add_llvm_target(RISCVCodeGen
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RISCVConstantPoolValue.cpp
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RISCVDeadRegisterDefinitions.cpp
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RISCVMakeCompressible.cpp
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RISCVLatePeephole.cpp
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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RISCVFoldMemOffset.cpp

llvm/lib/Target/RISCV/RISCV.h

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@@ -43,6 +43,9 @@ FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
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FunctionPass *createRISCVMakeCompressibleOptPass();
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void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
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FunctionPass *createRISCVLatePeepholeOptPass();
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void initializeRISCVLatePeepholeOptPass(PassRegistry &);
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FunctionPass *createRISCVGatherScatterLoweringPass();
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void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
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llvm/lib/Target/RISCV/RISCVInstrInfo.h

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@@ -306,19 +306,6 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
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static bool isLdStSafeToPair(const MachineInstr &LdSt,
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const TargetRegisterInfo *TRI);
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protected:
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const RISCVSubtarget &STI;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
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bool Invert = false) const;
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bool areRVVInstsReassociable(const MachineInstr &MI1,
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const MachineInstr &MI2) const;
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bool hasReassociableVectorSibling(const MachineInstr &Inst,
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bool &Commuted) const;
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/// Return true if the branch represented by the conditional branch with
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/// components TBB, FBB, and CurCond was folded into an unconditional branch.
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///
@@ -339,6 +326,19 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
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bool trySimplifyCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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protected:
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const RISCVSubtarget &STI;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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bool isVectorAssociativeAndCommutative(const MachineInstr &MI,
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bool Invert = false) const;
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bool areRVVInstsReassociable(const MachineInstr &MI1,
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const MachineInstr &MI2) const;
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bool hasReassociableVectorSibling(const MachineInstr &Inst,
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bool &Commuted) const;
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};
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namespace RISCV {
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//===-- RISCVLatePeephole.cpp - Late stage peephole optimization ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file provides RISC-V late peephole optimizations
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "RISCV.h"
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#include "RISCVInstrInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-late-peephole"
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#define RISCV_LATE_PEEPHOLE_NAME "RISC-V Late Stage Peephole"
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namespace {
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struct RISCVLatePeepholeOpt : public MachineFunctionPass {
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static char ID;
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RISCVLatePeepholeOpt() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return RISCV_LATE_PEEPHOLE_NAME; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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private:
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bool optimizeBlock(MachineBasicBlock &MBB);
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const RISCVInstrInfo *TII = nullptr;
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};
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} // namespace
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char RISCVLatePeepholeOpt::ID = 0;
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INITIALIZE_PASS(RISCVLatePeepholeOpt, "riscv-late-peephole",
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RISCV_LATE_PEEPHOLE_NAME, false, false)
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bool RISCVLatePeepholeOpt::optimizeBlock(MachineBasicBlock &MBB) {
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// Use trySimplifyCondBr directly to know whether the optimization occured.
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MachineBasicBlock *TBB, *FBB;
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SmallVector<MachineOperand, 4> Cond;
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if (!TII->analyzeBranch(MBB, TBB, FBB, Cond, false))
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return TII->trySimplifyCondBr(MBB, TBB, FBB, Cond);
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return false;
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}
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bool RISCVLatePeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
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bool MadeChange = false;
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for (MachineBasicBlock &MBB : MF)
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MadeChange |= optimizeBlock(MBB);
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return MadeChange;
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}
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/// Returns an instance of the Make Compressible Optimization pass.
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FunctionPass *llvm::createRISCVLatePeepholeOptPass() {
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return new RISCVLatePeepholeOpt();
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}

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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@@ -128,6 +128,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
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initializeKCFIPass(*PR);
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initializeRISCVDeadRegisterDefinitionsPass(*PR);
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initializeRISCVMakeCompressibleOptPass(*PR);
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initializeRISCVLatePeepholeOptPass(*PR);
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initializeRISCVGatherScatterLoweringPass(*PR);
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initializeRISCVCodeGenPreparePass(*PR);
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initializeRISCVPostRAExpandPseudoPass(*PR);
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addPass(createMachineCopyPropagationPass(true));
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addPass(&BranchRelaxationPassID);
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addPass(createRISCVMakeCompressibleOptPass());
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addPass(createRISCVLatePeepholeOptPass());
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}
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void RISCVPassConfig::addPreEmitPass2() {

llvm/test/CodeGen/RISCV/O0-pipeline.ll

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@@ -64,6 +64,7 @@
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: Branch relaxation pass
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; CHECK-NEXT: RISC-V Make Compressible
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; CHECK-NEXT: RISC-V Late Stage Peephole
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: Remove Loads Into Fake Uses
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; CHECK-NEXT: StackMap Liveness Analysis

llvm/test/CodeGen/RISCV/O3-pipeline.ll

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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Branch relaxation pass
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; CHECK-NEXT: RISC-V Make Compressible
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; CHECK-NEXT: RISC-V Late Stage Peephole
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: Remove Loads Into Fake Uses
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; CHECK-NEXT: StackMap Liveness Analysis

llvm/test/CodeGen/RISCV/simplify-condbr.ll

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@@ -128,7 +128,7 @@ define ptr @Perl_pp_refassign(ptr %PL_stack_sp, i1 %tobool.not, i1 %tobool3.not,
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; CHECK-NEXT: andi a2, a2, 1
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; CHECK-NEXT: beqz a2, .LBB1_2
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; CHECK-NEXT: .LBB1_4:
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; CHECK-NEXT: beqz zero, .LBB1_6
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; CHECK-NEXT: j .LBB1_6
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; CHECK-NEXT: .LBB1_5: # %sw.bb85
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill

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