@@ -820,7 +820,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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Inst.getOpcode () != AMDGPU::DS_CONSUME &&
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Inst.getOpcode () != AMDGPU::DS_ORDERED_COUNT) {
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for (const MachineOperand &Op : Inst.all_uses ()) {
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- if (Op. isReg () && TRI->isVectorRegister (*MRI, Op.getReg ()))
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+ if (TRI->isVectorRegister (*MRI, Op.getReg ()))
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setExpScore (&Inst, TRI, MRI, Op, CurrScore);
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}
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}
@@ -872,7 +872,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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}
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}
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for (const MachineOperand &Op : Inst.all_uses ()) {
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- if (Op. isReg () && TRI->isVectorRegister (*MRI, Op.getReg ()))
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+ if (TRI->isVectorRegister (*MRI, Op.getReg ()))
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setExpScore (&Inst, TRI, MRI, Op, CurrScore);
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}
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}
@@ -2327,7 +2327,7 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
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HasVMemStore = true ;
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}
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for (const MachineOperand &Op : MI.all_uses ()) {
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- if (!Op. isReg () || ! TRI->isVectorRegister (*MRI, Op.getReg ()))
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+ if (!TRI->isVectorRegister (*MRI, Op.getReg ()))
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continue ;
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RegInterval Interval = Brackets.getRegInterval (&MI, MRI, TRI, Op);
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// Vgpr use
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