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[AMDGPU] Omit isReg() check for all_uses() in SIInsertWaitcnts. NFC. (#109041)
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llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -820,7 +820,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
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Inst.getOpcode() != AMDGPU::DS_CONSUME &&
821821
Inst.getOpcode() != AMDGPU::DS_ORDERED_COUNT) {
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for (const MachineOperand &Op : Inst.all_uses()) {
823-
if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
823+
if (TRI->isVectorRegister(*MRI, Op.getReg()))
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setExpScore(&Inst, TRI, MRI, Op, CurrScore);
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}
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}
@@ -872,7 +872,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
872872
}
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}
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for (const MachineOperand &Op : Inst.all_uses()) {
875-
if (Op.isReg() && TRI->isVectorRegister(*MRI, Op.getReg()))
875+
if (TRI->isVectorRegister(*MRI, Op.getReg()))
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setExpScore(&Inst, TRI, MRI, Op, CurrScore);
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}
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}
@@ -2327,7 +2327,7 @@ bool SIInsertWaitcnts::shouldFlushVmCnt(MachineLoop *ML,
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HasVMemStore = true;
23282328
}
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for (const MachineOperand &Op : MI.all_uses()) {
2330-
if (!Op.isReg() || !TRI->isVectorRegister(*MRI, Op.getReg()))
2330+
if (!TRI->isVectorRegister(*MRI, Op.getReg()))
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continue;
23322332
RegInterval Interval = Brackets.getRegInterval(&MI, MRI, TRI, Op);
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// Vgpr use

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