Skip to content

Commit e112cb6

Browse files
topperctopperc
committed
[RISCV][GISel] Add regbank selection for G_FADD/G_FSUB/G_FMUL/G_FDIV with F/D extensions.
This includes the plumbing for ValueMapping and PartialMapping.
1 parent b379520 commit e112cb6

File tree

2 files changed

+223
-4
lines changed

2 files changed

+223
-4
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,12 +26,16 @@ namespace RISCV {
2626

2727
RegisterBankInfo::PartialMapping PartMappings[] = {
2828
{0, 32, GPRRegBank},
29-
{0, 64, GPRRegBank}
29+
{0, 64, GPRRegBank},
30+
{0, 32, FPRRegBank},
31+
{0, 64, FPRRegBank},
3032
};
3133

3234
enum PartialMappingIdx {
3335
PMI_GPR32 = 0,
34-
PMI_GPR64 = 1
36+
PMI_GPR64 = 1,
37+
PMI_FPR32 = 2,
38+
PMI_FPR64 = 3,
3539
};
3640

3741
RegisterBankInfo::ValueMapping ValueMappings[] = {
@@ -44,13 +48,23 @@ RegisterBankInfo::ValueMapping ValueMappings[] = {
4448
// Maximum 3 GPR operands; 64 bit.
4549
{&PartMappings[PMI_GPR64], 1},
4650
{&PartMappings[PMI_GPR64], 1},
47-
{&PartMappings[PMI_GPR64], 1}
51+
{&PartMappings[PMI_GPR64], 1},
52+
// Maximum 3 FPR operands; 32 bit.
53+
{&PartMappings[PMI_FPR32], 1},
54+
{&PartMappings[PMI_FPR32], 1},
55+
{&PartMappings[PMI_FPR32], 1},
56+
// Maximum 3 FPR operands; 64 bit.
57+
{&PartMappings[PMI_FPR64], 1},
58+
{&PartMappings[PMI_FPR64], 1},
59+
{&PartMappings[PMI_FPR64], 1},
4860
};
4961

5062
enum ValueMappingsIdx {
5163
InvalidIdx = 0,
5264
GPR32Idx = 1,
53-
GPR64Idx = 4
65+
GPR64Idx = 4,
66+
FPR32Idx = 7,
67+
FPR64Idx = 10,
5468
};
5569
} // namespace RISCV
5670
} // namespace llvm
@@ -101,6 +115,9 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
101115
return Mapping;
102116
}
103117

118+
const MachineFunction &MF = *MI.getParent()->getParent();
119+
const MachineRegisterInfo &MRI = MF.getRegInfo();
120+
104121
unsigned GPRSize = getMaximumSize(RISCV::GPRRegBankID);
105122
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
106123

@@ -158,6 +175,16 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
158175
OperandsMapping = getOperandsMapping(
159176
{GPRValueMapping, GPRValueMapping, GPRValueMapping, GPRValueMapping});
160177
break;
178+
case TargetOpcode::G_FADD:
179+
case TargetOpcode::G_FSUB:
180+
case TargetOpcode::G_FMUL:
181+
case TargetOpcode::G_FDIV: {
182+
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
183+
OperandsMapping = Ty.getSizeInBits() == 64
184+
? &RISCV::ValueMappings[RISCV::FPR64Idx]
185+
: &RISCV::ValueMappings[RISCV::FPR32Idx];
186+
break;
187+
}
161188
default:
162189
return getInvalidInstructionMapping();
163190
}

‎llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-arith.mir

Lines changed: 192 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,192 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=regbankselect \
3+
# RUN: -simplify-mir -verify-machineinstrs %s \
4+
# RUN: -o - | FileCheck %s
5+
# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=regbankselect \
6+
# RUN: -simplify-mir -verify-machineinstrs %s \
7+
# RUN: -o - | FileCheck %s
8+
9+
---
10+
name: fadd_f32
11+
legalized: true
12+
tracksRegLiveness: true
13+
body: |
14+
bb.0:
15+
liveins: $f10_f, $f11_f
16+
17+
; CHECK-LABEL: name: fadd_f32
18+
; CHECK: liveins: $f10_f, $f11_f
19+
; CHECK-NEXT: {{ $}}
20+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
21+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
22+
; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s32) = G_FADD [[COPY]], [[COPY1]]
23+
; CHECK-NEXT: $f10_f = COPY [[FADD]](s32)
24+
; CHECK-NEXT: PseudoRET implicit $f10_f
25+
%0:_(s32) = COPY $f10_f
26+
%1:_(s32) = COPY $f11_f
27+
%2:_(s32) = G_FADD %0, %1
28+
$f10_f = COPY %2(s32)
29+
PseudoRET implicit $f10_f
30+
31+
...
32+
---
33+
name: fsub_f32
34+
legalized: true
35+
tracksRegLiveness: true
36+
body: |
37+
bb.0:
38+
liveins: $f10_f, $f11_f
39+
40+
; CHECK-LABEL: name: fsub_f32
41+
; CHECK: liveins: $f10_f, $f11_f
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
44+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
45+
; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s32) = G_FSUB [[COPY]], [[COPY1]]
46+
; CHECK-NEXT: $f10_f = COPY [[FSUB]](s32)
47+
; CHECK-NEXT: PseudoRET implicit $f10_f
48+
%0:_(s32) = COPY $f10_f
49+
%1:_(s32) = COPY $f11_f
50+
%2:_(s32) = G_FSUB %0, %1
51+
$f10_f = COPY %2(s32)
52+
PseudoRET implicit $f10_f
53+
54+
...
55+
---
56+
name: fmul_f32
57+
legalized: true
58+
tracksRegLiveness: true
59+
body: |
60+
bb.0:
61+
liveins: $f10_f, $f11_f
62+
63+
; CHECK-LABEL: name: fmul_f32
64+
; CHECK: liveins: $f10_f, $f11_f
65+
; CHECK-NEXT: {{ $}}
66+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
67+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
68+
; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s32) = G_FMUL [[COPY]], [[COPY1]]
69+
; CHECK-NEXT: $f10_f = COPY [[FMUL]](s32)
70+
; CHECK-NEXT: PseudoRET implicit $f10_f
71+
%0:_(s32) = COPY $f10_f
72+
%1:_(s32) = COPY $f11_f
73+
%2:_(s32) = G_FMUL %0, %1
74+
$f10_f = COPY %2(s32)
75+
PseudoRET implicit $f10_f
76+
77+
...
78+
---
79+
name: fdiv_f32
80+
legalized: true
81+
tracksRegLiveness: true
82+
body: |
83+
bb.0:
84+
liveins: $f10_f, $f11_f
85+
86+
; CHECK-LABEL: name: fdiv_f32
87+
; CHECK: liveins: $f10_f, $f11_f
88+
; CHECK-NEXT: {{ $}}
89+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f10_f
90+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f11_f
91+
; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s32) = G_FDIV [[COPY]], [[COPY1]]
92+
; CHECK-NEXT: $f10_f = COPY [[FDIV]](s32)
93+
; CHECK-NEXT: PseudoRET implicit $f10_f
94+
%0:_(s32) = COPY $f10_f
95+
%1:_(s32) = COPY $f11_f
96+
%2:_(s32) = G_FDIV %0, %1
97+
$f10_f = COPY %2(s32)
98+
PseudoRET implicit $f10_f
99+
100+
...
101+
---
102+
name: fadd_f64
103+
legalized: true
104+
tracksRegLiveness: true
105+
body: |
106+
bb.0:
107+
liveins: $f10_d, $f11_d
108+
109+
; CHECK-LABEL: name: fadd_f64
110+
; CHECK: liveins: $f10_d, $f11_d
111+
; CHECK-NEXT: {{ $}}
112+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
113+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
114+
; CHECK-NEXT: [[FADD:%[0-9]+]]:fprb(s64) = G_FADD [[COPY]], [[COPY1]]
115+
; CHECK-NEXT: $f10_d = COPY [[FADD]](s64)
116+
; CHECK-NEXT: PseudoRET implicit $f10_d
117+
%0:_(s64) = COPY $f10_d
118+
%1:_(s64) = COPY $f11_d
119+
%2:_(s64) = G_FADD %0, %1
120+
$f10_d = COPY %2(s64)
121+
PseudoRET implicit $f10_d
122+
123+
...
124+
---
125+
name: fsub_f64
126+
legalized: true
127+
tracksRegLiveness: true
128+
body: |
129+
bb.0:
130+
liveins: $f10_d, $f11_d
131+
132+
; CHECK-LABEL: name: fsub_f64
133+
; CHECK: liveins: $f10_d, $f11_d
134+
; CHECK-NEXT: {{ $}}
135+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
136+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
137+
; CHECK-NEXT: [[FSUB:%[0-9]+]]:fprb(s64) = G_FSUB [[COPY]], [[COPY1]]
138+
; CHECK-NEXT: $f10_d = COPY [[FSUB]](s64)
139+
; CHECK-NEXT: PseudoRET implicit $f10_d
140+
%0:_(s64) = COPY $f10_d
141+
%1:_(s64) = COPY $f11_d
142+
%2:_(s64) = G_FSUB %0, %1
143+
$f10_d = COPY %2(s64)
144+
PseudoRET implicit $f10_d
145+
146+
...
147+
---
148+
name: fmul_f64
149+
legalized: true
150+
tracksRegLiveness: true
151+
body: |
152+
bb.0:
153+
liveins: $f10_d, $f11_d
154+
155+
; CHECK-LABEL: name: fmul_f64
156+
; CHECK: liveins: $f10_d, $f11_d
157+
; CHECK-NEXT: {{ $}}
158+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
159+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
160+
; CHECK-NEXT: [[FMUL:%[0-9]+]]:fprb(s64) = G_FMUL [[COPY]], [[COPY1]]
161+
; CHECK-NEXT: $f10_d = COPY [[FMUL]](s64)
162+
; CHECK-NEXT: PseudoRET implicit $f10_d
163+
%0:_(s64) = COPY $f10_d
164+
%1:_(s64) = COPY $f11_d
165+
%2:_(s64) = G_FMUL %0, %1
166+
$f10_d = COPY %2(s64)
167+
PseudoRET implicit $f10_d
168+
169+
...
170+
---
171+
name: fdiv_f64
172+
legalized: true
173+
tracksRegLiveness: true
174+
body: |
175+
bb.0:
176+
liveins: $f10_d, $f11_d
177+
178+
; CHECK-LABEL: name: fdiv_f64
179+
; CHECK: liveins: $f10_d, $f11_d
180+
; CHECK-NEXT: {{ $}}
181+
; CHECK-NEXT: [[COPY:%[0-9]+]]:fprb(s64) = COPY $f10_d
182+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fprb(s64) = COPY $f11_d
183+
; CHECK-NEXT: [[FDIV:%[0-9]+]]:fprb(s64) = G_FDIV [[COPY]], [[COPY1]]
184+
; CHECK-NEXT: $f10_d = COPY [[FDIV]](s64)
185+
; CHECK-NEXT: PseudoRET implicit $f10_d
186+
%0:_(s64) = COPY $f10_d
187+
%1:_(s64) = COPY $f11_d
188+
%2:_(s64) = G_FDIV %0, %1
189+
$f10_d = COPY %2(s64)
190+
PseudoRET implicit $f10_d
191+
192+
...

0 commit comments

Comments
 (0)