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1 parent c6472f5 commit e145bc4Copy full SHA for e145bc4
llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -61,8 +61,8 @@ static_library("LLVMRISCVCodeGen") {
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":RISCVGenCompressInstEmitter",
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":RISCVGenDAGISel",
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":RISCVGenGlobalISel",
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- ":RISCVGenO0PreLegalizeGICombiner",
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":RISCVGenMCPseudoLowering",
+ ":RISCVGenO0PreLegalizeGICombiner",
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":RISCVGenPreLegalizeGICombiner",
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":RISCVGenRegisterBank",
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@@ -92,6 +92,7 @@ static_library("LLVMRISCVCodeGen") {
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"GISel/RISCVRegisterBankInfo.cpp",
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"RISCVAsmPrinter.cpp",
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"RISCVCodeGenPrepare.cpp",
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+ "RISCVDeadRegisterDefinitions.cpp",
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"RISCVExpandAtomicPseudoInsts.cpp",
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"RISCVExpandPseudoInsts.cpp",
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"RISCVFrameLowering.cpp",
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