Skip to content

Commit e16a215

Browse files
committed
Move GlobalISel changes from x86 to aarch64
1 parent 413af24 commit e16a215

File tree

3 files changed

+7
-0
lines changed

3 files changed

+7
-0
lines changed

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -155,6 +155,7 @@ def : GINodeEquiv<G_FTAN, ftan>;
155155
def : GINodeEquiv<G_FACOS, facos>;
156156
def : GINodeEquiv<G_FASIN, fasin>;
157157
def : GINodeEquiv<G_FATAN, fatan>;
158+
def : GINodeEquiv<G_FATAN2, fatan2>;
158159
def : GINodeEquiv<G_FCOSH, fcosh>;
159160
def : GINodeEquiv<G_FSINH, fsinh>;
160161
def : GINodeEquiv<G_FTANH, ftanh>;

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -457,6 +457,8 @@ static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
457457
RTLIBCASE(ACOS_F);
458458
case TargetOpcode::G_FATAN:
459459
RTLIBCASE(ATAN_F);
460+
case TargetOpcode::G_FATAN2:
461+
RTLIBCASE(ATAN2_F);
460462
case TargetOpcode::G_FSINH:
461463
RTLIBCASE(SINH_F);
462464
case TargetOpcode::G_FCOSH:
@@ -1202,6 +1204,7 @@ LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) {
12021204
case TargetOpcode::G_FACOS:
12031205
case TargetOpcode::G_FASIN:
12041206
case TargetOpcode::G_FATAN:
1207+
case TargetOpcode::G_FATAN2:
12051208
case TargetOpcode::G_FCOSH:
12061209
case TargetOpcode::G_FSINH:
12071210
case TargetOpcode::G_FTANH:
@@ -3122,6 +3125,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
31223125
case TargetOpcode::G_FACOS:
31233126
case TargetOpcode::G_FASIN:
31243127
case TargetOpcode::G_FATAN:
3128+
case TargetOpcode::G_FATAN2:
31253129
case TargetOpcode::G_FCOSH:
31263130
case TargetOpcode::G_FSINH:
31273131
case TargetOpcode::G_FTANH:

llvm/lib/CodeGen/GlobalISel/Utils.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -828,6 +828,7 @@ bool llvm::isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
828828
case TargetOpcode::G_FACOS:
829829
case TargetOpcode::G_FASIN:
830830
case TargetOpcode::G_FATAN:
831+
case TargetOpcode::G_FATAN2:
831832
case TargetOpcode::G_FCOSH:
832833
case TargetOpcode::G_FSINH:
833834
case TargetOpcode::G_FTANH:
@@ -1715,6 +1716,7 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) {
17151716
case TargetOpcode::G_FACOS:
17161717
case TargetOpcode::G_FASIN:
17171718
case TargetOpcode::G_FATAN:
1719+
case TargetOpcode::G_FATAN2:
17181720
case TargetOpcode::G_FCOSH:
17191721
case TargetOpcode::G_FSINH:
17201722
case TargetOpcode::G_FTANH:

0 commit comments

Comments
 (0)