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[SelectionDAG] Fix a false assumption that there will always be a valid integer type corresponding to a vector type
`SelectionDAG::getBitcastedAnyExtOrTrunc` assumes that there is always a valid integer type corresponding to another type, which is not always true when it comes to vector type. For example, `<3 x i8>` doesn't have a corresponding integer type. Fix SWDEV-464698.
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llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1468,13 +1468,30 @@ SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
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}
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SDValue SelectionDAG::getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL,
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EVT VT) {
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EVT VT) {
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assert(!VT.isVector());
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auto Type = Op.getValueType();
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SDValue DestOp;
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if (Type == VT)
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return Op;
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auto Size = Op.getValueSizeInBits();
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auto IntTy = MVT::getIntegerVT(Size);
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if (!IntTy.isValid()) {
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// We assume integers of "weird" size have already been legalized here.
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assert(Type.isVector());
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unsigned NumElements = Type.getVectorNumElements();
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unsigned ExtSize = VT.getScalarSizeInBits();
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EVT ElementType = Type.getVectorElementType();
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unsigned ExtNumElements = ExtSize / ElementType.getScalarSizeInBits();
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assert(NumElements < ExtNumElements);
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MVT ExtType = MVT::getVectorVT(ElementType.getSimpleVT(), ExtNumElements);
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SDValue ExtVec = getUNDEF(ExtType);
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DestOp = getNode(ISD::INSERT_SUBVECTOR, DL, ExtType, ExtVec, Op,
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getVectorIdxConstant(0, DL));
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return getBitcast(VT, DestOp);
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}
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DestOp = getBitcast(MVT::getIntegerVT(Size), Op);
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if (DestOp.getValueType() == VT)
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return DestOp;
Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s -o - | FileCheck %s
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define void @no_corresponding_integer_type(i8 %arg, ptr addrspace(1) %ptr) {
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; CHECK-LABEL: no_corresponding_integer_type:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v3, v2
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; CHECK-NEXT: v_mov_b32_e32 v2, v1
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; CHECK-NEXT: global_load_ushort v1, v[2:3], off
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; CHECK-NEXT: global_load_ubyte v4, v[2:3], off offset:2
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; CHECK-NEXT: s_mov_b32 s0, 0xc0c0400
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; CHECK-NEXT: s_mov_b32 s1, 0xc0c0000
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_lshl_or_b32 v1, v4, 16, v1
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; CHECK-NEXT: v_perm_b32 v1, v0, v1, s0
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; CHECK-NEXT: v_perm_b32 v0, v0, v0, s1
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; CHECK-NEXT: v_dot4_u32_u8 v0, v0, v1, 1
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; CHECK-NEXT: s_nop 2
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; CHECK-NEXT: global_store_byte v[2:3], v0, off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%load = load <3 x i8>, ptr addrspace(1) %ptr, align 1
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%elt0 = extractelement <3 x i8> %load, i64 0
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%mul0 = mul i8 %elt0, %arg
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%or = or i8 %mul0, 1
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%mul1 = mul i8 %arg, %arg
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%add = add i8 %mul1, %or
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store i8 %add, ptr addrspace(1) %ptr, align 1
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ret void
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}

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