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3 files changed

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-138
lines changed

3 files changed

+120
-138
lines changed

‎llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -914,16 +914,12 @@ bool TwoAddressInstructionPass::rescheduleMIBelowKill(
914914
}
915915

916916
// Check if the reschedule will not break dependencies.
917-
unsigned NumVisited = 0;
918917
MachineBasicBlock::iterator KillPos = KillMI;
919918
++KillPos;
920919
for (MachineInstr &OtherMI : make_range(End, KillPos)) {
921920
// Debug or pseudo instructions cannot be counted against the limit.
922921
if (OtherMI.isDebugOrPseudoInstr())
923922
continue;
924-
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
925-
return false;
926-
++NumVisited;
927923
if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
928924
OtherMI.isBranch() || OtherMI.isTerminator())
929925
// Don't move pass calls, etc.
@@ -1088,15 +1084,11 @@ bool TwoAddressInstructionPass::rescheduleKillAboveMI(
10881084
}
10891085

10901086
// Check if the reschedule will not break depedencies.
1091-
unsigned NumVisited = 0;
10921087
for (MachineInstr &OtherMI :
10931088
make_range(mi, MachineBasicBlock::iterator(KillMI))) {
10941089
// Debug or pseudo instructions cannot be counted against the limit.
10951090
if (OtherMI.isDebugOrPseudoInstr())
10961091
continue;
1097-
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1098-
return false;
1099-
++NumVisited;
11001092
if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
11011093
OtherMI.isBranch() || OtherMI.isTerminator())
11021094
// Don't move pass calls, etc.

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll

Lines changed: 88 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -236,22 +236,20 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
236236
; CHECK-NEXT: sunpklo z4.d, z2.s
237237
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
238238
; CHECK-NEXT: sunpklo z0.s, z0.h
239-
; CHECK-NEXT: mov z7.d, z1.d
240-
; CHECK-NEXT: sunpklo z2.d, z2.s
239+
; CHECK-NEXT: sunpklo z7.d, z1.s
240+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
241241
; CHECK-NEXT: sunpklo z5.d, z3.s
242242
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
243-
; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8
243+
; CHECK-NEXT: sunpklo z2.d, z2.s
244244
; CHECK-NEXT: sunpklo z1.d, z1.s
245-
; CHECK-NEXT: mov z6.d, z0.d
245+
; CHECK-NEXT: sunpklo z6.d, z0.s
246+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
246247
; CHECK-NEXT: sunpklo z3.d, z3.s
247248
; CHECK-NEXT: stp q4, q2, [x0]
248-
; CHECK-NEXT: sunpklo z4.d, z7.s
249-
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
250249
; CHECK-NEXT: sunpklo z0.d, z0.s
250+
; CHECK-NEXT: stp q7, q1, [x0, #32]
251251
; CHECK-NEXT: stp q5, q3, [x0, #64]
252-
; CHECK-NEXT: sunpklo z2.d, z6.s
253-
; CHECK-NEXT: stp q1, q4, [x0, #32]
254-
; CHECK-NEXT: stp q0, q2, [x0, #96]
252+
; CHECK-NEXT: stp q6, q0, [x0, #96]
255253
; CHECK-NEXT: ret
256254
%b = sext <16 x i8> %a to <16 x i64>
257255
store <16 x i64> %b, ptr %out
@@ -264,62 +262,60 @@ define void @sext_v32i8_v32i64(ptr %in, ptr %out) {
264262
; CHECK-NEXT: ldp q1, q0, [x0]
265263
; CHECK-NEXT: add z0.b, z0.b, z0.b
266264
; CHECK-NEXT: add z1.b, z1.b, z1.b
267-
; CHECK-NEXT: mov z2.d, z0.d
265+
; CHECK-NEXT: sunpklo z2.h, z0.b
266+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
267+
; CHECK-NEXT: sunpklo z3.h, z1.b
268+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
268269
; CHECK-NEXT: sunpklo z0.h, z0.b
269-
; CHECK-NEXT: mov z3.d, z1.d
270+
; CHECK-NEXT: sunpklo z4.s, z2.h
270271
; CHECK-NEXT: sunpklo z1.h, z1.b
272+
; CHECK-NEXT: sunpklo z5.s, z3.h
271273
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
272274
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
273-
; CHECK-NEXT: sunpklo z4.s, z0.h
275+
; CHECK-NEXT: sunpklo z6.s, z0.h
274276
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
275-
; CHECK-NEXT: sunpklo z5.s, z1.h
276-
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
277-
; CHECK-NEXT: sunpklo z2.h, z2.b
278-
; CHECK-NEXT: sunpklo z3.h, z3.b
279-
; CHECK-NEXT: sunpklo z0.s, z0.h
280-
; CHECK-NEXT: sunpklo z16.d, z4.s
277+
; CHECK-NEXT: sunpklo z7.d, z4.s
281278
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
282-
; CHECK-NEXT: sunpklo z1.s, z1.h
279+
; CHECK-NEXT: sunpklo z2.s, z2.h
280+
; CHECK-NEXT: sunpklo z3.s, z3.h
281+
; CHECK-NEXT: sunpklo z16.s, z1.h
283282
; CHECK-NEXT: sunpklo z17.d, z5.s
284283
; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8
285-
; CHECK-NEXT: sunpklo z6.s, z2.h
286-
; CHECK-NEXT: sunpklo z7.s, z3.h
287-
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
284+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
285+
; CHECK-NEXT: sunpklo z0.s, z0.h
288286
; CHECK-NEXT: sunpklo z4.d, z4.s
289-
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
290-
; CHECK-NEXT: sunpklo z19.d, z0.s
291-
; CHECK-NEXT: sunpklo z5.d, z5.s
292-
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
293-
; CHECK-NEXT: sunpklo z2.s, z2.h
294287
; CHECK-NEXT: sunpklo z18.d, z6.s
295288
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
296-
; CHECK-NEXT: sunpklo z3.s, z3.h
297-
; CHECK-NEXT: stp q16, q4, [x1, #128]
298-
; CHECK-NEXT: mov z16.d, z7.d
299-
; CHECK-NEXT: sunpklo z0.d, z0.s
300-
; CHECK-NEXT: stp q17, q5, [x1]
301-
; CHECK-NEXT: sunpklo z5.d, z7.s
302-
; CHECK-NEXT: sunpklo z4.d, z6.s
303-
; CHECK-NEXT: mov z6.d, z1.d
304-
; CHECK-NEXT: ext z16.b, z16.b, z7.b, #8
289+
; CHECK-NEXT: sunpklo z5.d, z5.s
290+
; CHECK-NEXT: sunpklo z1.s, z1.h
291+
; CHECK-NEXT: sunpklo z19.d, z16.s
292+
; CHECK-NEXT: sunpklo z6.d, z6.s
293+
; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8
294+
; CHECK-NEXT: stp q7, q4, [x1, #128]
305295
; CHECK-NEXT: mov z7.d, z2.d
306-
; CHECK-NEXT: stp q19, q0, [x1, #160]
307-
; CHECK-NEXT: sunpklo z0.d, z2.s
308-
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
309-
; CHECK-NEXT: sunpklo z1.d, z1.s
310-
; CHECK-NEXT: stp q18, q4, [x1, #192]
311296
; CHECK-NEXT: mov z4.d, z3.d
312-
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
297+
; CHECK-NEXT: stp q17, q5, [x1]
298+
; CHECK-NEXT: mov z5.d, z0.d
313299
; CHECK-NEXT: sunpklo z16.d, z16.s
314-
; CHECK-NEXT: sunpklo z6.d, z6.s
300+
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
315301
; CHECK-NEXT: ext z4.b, z4.b, z3.b, #8
316-
; CHECK-NEXT: sunpklo z2.d, z7.s
302+
; CHECK-NEXT: stp q18, q6, [x1, #192]
303+
; CHECK-NEXT: mov z6.d, z1.d
304+
; CHECK-NEXT: sunpklo z2.d, z2.s
317305
; CHECK-NEXT: sunpklo z3.d, z3.s
318-
; CHECK-NEXT: stp q5, q16, [x1, #64]
319-
; CHECK-NEXT: stp q1, q6, [x1, #32]
320-
; CHECK-NEXT: sunpklo z1.d, z4.s
306+
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
307+
; CHECK-NEXT: sunpklo z0.d, z0.s
308+
; CHECK-NEXT: sunpklo z7.d, z7.s
309+
; CHECK-NEXT: sunpklo z4.d, z4.s
310+
; CHECK-NEXT: stp q19, q16, [x1, #64]
311+
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
312+
; CHECK-NEXT: sunpklo z1.d, z1.s
313+
; CHECK-NEXT: stp q3, q4, [x1, #32]
314+
; CHECK-NEXT: sunpklo z3.d, z6.s
315+
; CHECK-NEXT: stp q2, q7, [x1, #160]
316+
; CHECK-NEXT: sunpklo z2.d, z5.s
317+
; CHECK-NEXT: stp q1, q3, [x1, #96]
321318
; CHECK-NEXT: stp q0, q2, [x1, #224]
322-
; CHECK-NEXT: stp q3, q1, [x1, #96]
323319
; CHECK-NEXT: ret
324320
%a = load <32 x i8>, ptr %in
325321
%b = add <32 x i8> %a, %a
@@ -661,22 +657,20 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
661657
; CHECK-NEXT: uunpklo z4.d, z2.s
662658
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
663659
; CHECK-NEXT: uunpklo z0.s, z0.h
664-
; CHECK-NEXT: mov z7.d, z1.d
665-
; CHECK-NEXT: uunpklo z2.d, z2.s
660+
; CHECK-NEXT: uunpklo z7.d, z1.s
661+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
666662
; CHECK-NEXT: uunpklo z5.d, z3.s
667663
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
668-
; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8
664+
; CHECK-NEXT: uunpklo z2.d, z2.s
669665
; CHECK-NEXT: uunpklo z1.d, z1.s
670-
; CHECK-NEXT: mov z6.d, z0.d
666+
; CHECK-NEXT: uunpklo z6.d, z0.s
667+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
671668
; CHECK-NEXT: uunpklo z3.d, z3.s
672669
; CHECK-NEXT: stp q4, q2, [x0]
673-
; CHECK-NEXT: uunpklo z4.d, z7.s
674-
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
675670
; CHECK-NEXT: uunpklo z0.d, z0.s
671+
; CHECK-NEXT: stp q7, q1, [x0, #32]
676672
; CHECK-NEXT: stp q5, q3, [x0, #64]
677-
; CHECK-NEXT: uunpklo z2.d, z6.s
678-
; CHECK-NEXT: stp q1, q4, [x0, #32]
679-
; CHECK-NEXT: stp q0, q2, [x0, #96]
673+
; CHECK-NEXT: stp q6, q0, [x0, #96]
680674
; CHECK-NEXT: ret
681675
%b = zext <16 x i8> %a to <16 x i64>
682676
store <16 x i64> %b, ptr %out
@@ -689,62 +683,60 @@ define void @zext_v32i8_v32i64(ptr %in, ptr %out) {
689683
; CHECK-NEXT: ldp q1, q0, [x0]
690684
; CHECK-NEXT: add z0.b, z0.b, z0.b
691685
; CHECK-NEXT: add z1.b, z1.b, z1.b
692-
; CHECK-NEXT: mov z2.d, z0.d
686+
; CHECK-NEXT: uunpklo z2.h, z0.b
687+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
688+
; CHECK-NEXT: uunpklo z3.h, z1.b
689+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
693690
; CHECK-NEXT: uunpklo z0.h, z0.b
694-
; CHECK-NEXT: mov z3.d, z1.d
691+
; CHECK-NEXT: uunpklo z4.s, z2.h
695692
; CHECK-NEXT: uunpklo z1.h, z1.b
693+
; CHECK-NEXT: uunpklo z5.s, z3.h
696694
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
697695
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
698-
; CHECK-NEXT: uunpklo z4.s, z0.h
696+
; CHECK-NEXT: uunpklo z6.s, z0.h
699697
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
700-
; CHECK-NEXT: uunpklo z5.s, z1.h
701-
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
702-
; CHECK-NEXT: uunpklo z2.h, z2.b
703-
; CHECK-NEXT: uunpklo z3.h, z3.b
704-
; CHECK-NEXT: uunpklo z0.s, z0.h
705-
; CHECK-NEXT: uunpklo z16.d, z4.s
698+
; CHECK-NEXT: uunpklo z7.d, z4.s
706699
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
707-
; CHECK-NEXT: uunpklo z1.s, z1.h
700+
; CHECK-NEXT: uunpklo z2.s, z2.h
701+
; CHECK-NEXT: uunpklo z3.s, z3.h
702+
; CHECK-NEXT: uunpklo z16.s, z1.h
708703
; CHECK-NEXT: uunpklo z17.d, z5.s
709704
; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8
710-
; CHECK-NEXT: uunpklo z6.s, z2.h
711-
; CHECK-NEXT: uunpklo z7.s, z3.h
712-
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
705+
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
706+
; CHECK-NEXT: uunpklo z0.s, z0.h
713707
; CHECK-NEXT: uunpklo z4.d, z4.s
714-
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
715-
; CHECK-NEXT: uunpklo z19.d, z0.s
716-
; CHECK-NEXT: uunpklo z5.d, z5.s
717-
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
718-
; CHECK-NEXT: uunpklo z2.s, z2.h
719708
; CHECK-NEXT: uunpklo z18.d, z6.s
720709
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
721-
; CHECK-NEXT: uunpklo z3.s, z3.h
722-
; CHECK-NEXT: stp q16, q4, [x1, #128]
723-
; CHECK-NEXT: mov z16.d, z7.d
724-
; CHECK-NEXT: uunpklo z0.d, z0.s
725-
; CHECK-NEXT: stp q17, q5, [x1]
726-
; CHECK-NEXT: uunpklo z5.d, z7.s
727-
; CHECK-NEXT: uunpklo z4.d, z6.s
728-
; CHECK-NEXT: mov z6.d, z1.d
729-
; CHECK-NEXT: ext z16.b, z16.b, z7.b, #8
710+
; CHECK-NEXT: uunpklo z5.d, z5.s
711+
; CHECK-NEXT: uunpklo z1.s, z1.h
712+
; CHECK-NEXT: uunpklo z19.d, z16.s
713+
; CHECK-NEXT: uunpklo z6.d, z6.s
714+
; CHECK-NEXT: ext z16.b, z16.b, z16.b, #8
715+
; CHECK-NEXT: stp q7, q4, [x1, #128]
730716
; CHECK-NEXT: mov z7.d, z2.d
731-
; CHECK-NEXT: stp q19, q0, [x1, #160]
732-
; CHECK-NEXT: uunpklo z0.d, z2.s
733-
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
734-
; CHECK-NEXT: uunpklo z1.d, z1.s
735-
; CHECK-NEXT: stp q18, q4, [x1, #192]
736717
; CHECK-NEXT: mov z4.d, z3.d
737-
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
718+
; CHECK-NEXT: stp q17, q5, [x1]
719+
; CHECK-NEXT: mov z5.d, z0.d
738720
; CHECK-NEXT: uunpklo z16.d, z16.s
739-
; CHECK-NEXT: uunpklo z6.d, z6.s
721+
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
740722
; CHECK-NEXT: ext z4.b, z4.b, z3.b, #8
741-
; CHECK-NEXT: uunpklo z2.d, z7.s
723+
; CHECK-NEXT: stp q18, q6, [x1, #192]
724+
; CHECK-NEXT: mov z6.d, z1.d
725+
; CHECK-NEXT: uunpklo z2.d, z2.s
742726
; CHECK-NEXT: uunpklo z3.d, z3.s
743-
; CHECK-NEXT: stp q5, q16, [x1, #64]
744-
; CHECK-NEXT: stp q1, q6, [x1, #32]
745-
; CHECK-NEXT: uunpklo z1.d, z4.s
727+
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
728+
; CHECK-NEXT: uunpklo z0.d, z0.s
729+
; CHECK-NEXT: uunpklo z7.d, z7.s
730+
; CHECK-NEXT: uunpklo z4.d, z4.s
731+
; CHECK-NEXT: stp q19, q16, [x1, #64]
732+
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
733+
; CHECK-NEXT: uunpklo z1.d, z1.s
734+
; CHECK-NEXT: stp q3, q4, [x1, #32]
735+
; CHECK-NEXT: uunpklo z3.d, z6.s
736+
; CHECK-NEXT: stp q2, q7, [x1, #160]
737+
; CHECK-NEXT: uunpklo z2.d, z5.s
738+
; CHECK-NEXT: stp q1, q3, [x1, #96]
746739
; CHECK-NEXT: stp q0, q2, [x1, #224]
747-
; CHECK-NEXT: stp q3, q1, [x1, #96]
748740
; CHECK-NEXT: ret
749741
%a = load <32 x i8>, ptr %in
750742
%b = add <32 x i8> %a, %a

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll

Lines changed: 32 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -207,36 +207,35 @@ define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) {
207207
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
208208
; CHECK-NEXT: uunpklo z0.s, z0.h
209209
; CHECK-NEXT: uunpklo z1.s, z1.h
210-
; CHECK-NEXT: mov z4.d, z2.d
210+
; CHECK-NEXT: uunpklo z4.d, z2.s
211+
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
211212
; CHECK-NEXT: mov z7.d, z3.d
212-
; CHECK-NEXT: mov z5.d, z0.d
213-
; CHECK-NEXT: ext z4.b, z4.b, z2.b, #8
213+
; CHECK-NEXT: uunpklo z5.d, z0.s
214+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
214215
; CHECK-NEXT: uunpklo z2.d, z2.s
215216
; CHECK-NEXT: mov z6.d, z1.d
217+
; CHECK-NEXT: ucvtf z4.d, p0/m, z4.d
216218
; CHECK-NEXT: ext z7.b, z7.b, z3.b, #8
217219
; CHECK-NEXT: uunpklo z3.d, z3.s
218-
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
219-
; CHECK-NEXT: uunpklo z4.d, z4.s
220220
; CHECK-NEXT: uunpklo z0.d, z0.s
221221
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
222222
; CHECK-NEXT: uunpklo z1.d, z1.s
223223
; CHECK-NEXT: ucvtf z2.d, p0/m, z2.d
224-
; CHECK-NEXT: ucvtf z3.d, p0/m, z3.d
224+
; CHECK-NEXT: ucvtf z5.d, p0/m, z5.d
225225
; CHECK-NEXT: uunpklo z7.d, z7.s
226-
; CHECK-NEXT: uunpklo z5.d, z5.s
227-
; CHECK-NEXT: ucvtf z4.d, p0/m, z4.d
228226
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
229227
; CHECK-NEXT: uunpklo z6.d, z6.s
230228
; CHECK-NEXT: ucvtf z1.d, p0/m, z1.d
231-
; CHECK-NEXT: ucvtf z5.d, p0/m, z5.d
232-
; CHECK-NEXT: stp q2, q4, [x1, #64]
233-
; CHECK-NEXT: movprfx z2, z6
234-
; CHECK-NEXT: ucvtf z2.d, p0/m, z6.d
235-
; CHECK-NEXT: stp q1, q2, [x1, #32]
236-
; CHECK-NEXT: stp q0, q5, [x1, #96]
237-
; CHECK-NEXT: movprfx z0, z7
238-
; CHECK-NEXT: ucvtf z0.d, p0/m, z7.d
239-
; CHECK-NEXT: stp q3, q0, [x1]
229+
; CHECK-NEXT: stp q4, q2, [x1, #64]
230+
; CHECK-NEXT: movprfx z4, z6
231+
; CHECK-NEXT: ucvtf z4.d, p0/m, z6.d
232+
; CHECK-NEXT: movprfx z2, z3
233+
; CHECK-NEXT: ucvtf z2.d, p0/m, z3.d
234+
; CHECK-NEXT: movprfx z3, z7
235+
; CHECK-NEXT: ucvtf z3.d, p0/m, z7.d
236+
; CHECK-NEXT: stp q2, q3, [x1]
237+
; CHECK-NEXT: stp q5, q0, [x1, #96]
238+
; CHECK-NEXT: stp q1, q4, [x1, #32]
240239
; CHECK-NEXT: ret
241240
%op1 = load <16 x i16>, ptr %a
242241
%res = uitofp <16 x i16> %op1 to <16 x double>
@@ -780,36 +779,35 @@ define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) {
780779
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
781780
; CHECK-NEXT: sunpklo z0.s, z0.h
782781
; CHECK-NEXT: sunpklo z1.s, z1.h
783-
; CHECK-NEXT: mov z4.d, z2.d
782+
; CHECK-NEXT: sunpklo z4.d, z2.s
783+
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
784784
; CHECK-NEXT: mov z7.d, z3.d
785-
; CHECK-NEXT: mov z5.d, z0.d
786-
; CHECK-NEXT: ext z4.b, z4.b, z2.b, #8
785+
; CHECK-NEXT: sunpklo z5.d, z0.s
786+
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
787787
; CHECK-NEXT: sunpklo z2.d, z2.s
788788
; CHECK-NEXT: mov z6.d, z1.d
789+
; CHECK-NEXT: scvtf z4.d, p0/m, z4.d
789790
; CHECK-NEXT: ext z7.b, z7.b, z3.b, #8
790791
; CHECK-NEXT: sunpklo z3.d, z3.s
791-
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
792-
; CHECK-NEXT: sunpklo z4.d, z4.s
793792
; CHECK-NEXT: sunpklo z0.d, z0.s
794793
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
795794
; CHECK-NEXT: sunpklo z1.d, z1.s
796795
; CHECK-NEXT: scvtf z2.d, p0/m, z2.d
797-
; CHECK-NEXT: scvtf z3.d, p0/m, z3.d
796+
; CHECK-NEXT: scvtf z5.d, p0/m, z5.d
798797
; CHECK-NEXT: sunpklo z7.d, z7.s
799-
; CHECK-NEXT: sunpklo z5.d, z5.s
800-
; CHECK-NEXT: scvtf z4.d, p0/m, z4.d
801798
; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
802799
; CHECK-NEXT: sunpklo z6.d, z6.s
803800
; CHECK-NEXT: scvtf z1.d, p0/m, z1.d
804-
; CHECK-NEXT: scvtf z5.d, p0/m, z5.d
805-
; CHECK-NEXT: stp q2, q4, [x1, #64]
806-
; CHECK-NEXT: movprfx z2, z6
807-
; CHECK-NEXT: scvtf z2.d, p0/m, z6.d
808-
; CHECK-NEXT: stp q1, q2, [x1, #32]
809-
; CHECK-NEXT: stp q0, q5, [x1, #96]
810-
; CHECK-NEXT: movprfx z0, z7
811-
; CHECK-NEXT: scvtf z0.d, p0/m, z7.d
812-
; CHECK-NEXT: stp q3, q0, [x1]
801+
; CHECK-NEXT: stp q4, q2, [x1, #64]
802+
; CHECK-NEXT: movprfx z4, z6
803+
; CHECK-NEXT: scvtf z4.d, p0/m, z6.d
804+
; CHECK-NEXT: movprfx z2, z3
805+
; CHECK-NEXT: scvtf z2.d, p0/m, z3.d
806+
; CHECK-NEXT: movprfx z3, z7
807+
; CHECK-NEXT: scvtf z3.d, p0/m, z7.d
808+
; CHECK-NEXT: stp q2, q3, [x1]
809+
; CHECK-NEXT: stp q5, q0, [x1, #96]
810+
; CHECK-NEXT: stp q1, q4, [x1, #32]
813811
; CHECK-NEXT: ret
814812
%op1 = load <16 x i16>, ptr %a
815813
%res = sitofp <16 x i16> %op1 to <16 x double>

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