!fixup Use constrainRegClass

Author: BeMg

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -565,11 +565,6 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
   if (MI.getOperand(1).getReg() != RISCV::NoRegister)
     return false;
 
-  const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
-  const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
-  if (!RC1->hasSubClassEq(RC2))
-    return false;
-
   // If the input was a pseudo with a policy operand, we can give it a tail
   // agnostic policy if MI's undef tail subsumes the input's.
   MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
@@ -588,6 +583,8 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
       SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
   }
 
+  MRI->constrainRegClass(MI.getOperand(2).getReg(),
+                         MRI->getRegClass(MI.getOperand(0).getReg()));
   MRI->replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
   MI.eraseFromParent();
   return true;
@@ -612,11 +609,6 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
   if (!MRI->hasOneUse(MI.getOperand(2).getReg()))
     return false;
 
-  const TargetRegisterClass *RC1 = MRI->getRegClass(MI.getOperand(0).getReg());
-  const TargetRegisterClass *RC2 = MRI->getRegClass(MI.getOperand(2).getReg());
-  if (!RC1->hasSubClassEq(RC2))
-    return false;
-
   MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
   if (!Src || Src->hasUnmodeledSideEffects() ||
       Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
@@ -662,6 +654,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
     Policy |= RISCVVType::TAIL_AGNOSTIC;
   Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
 
+  MRI->constrainRegClass(Src->getOperand(0).getReg(),
+                         MRI->getRegClass(MI.getOperand(0).getReg()));
   MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
   MI.eraseFromParent();
 

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

@@ -98,10 +98,9 @@ body:             |
     ; CHECK-LABEL: name: diff_regclass
     ; CHECK: liveins: $v8
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
-    ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 $noreg, [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
-    ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVXOR_VV_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVXOR_VV_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[PseudoVMV_V_I_MF2_]], [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
     %0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
     %1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
     %4:vmv0 = COPY $v8
@@ -116,11 +115,10 @@ body:             |
     ; CHECK: liveins: $v8
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
-    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 0 /* tu, mu */
-    ; CHECK-NEXT: [[PseudoVMV_V_V_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_V_MF2 [[COPY]], killed [[PseudoVMV_V_I_MF2_]], 0, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 [[COPY]], 0, 0, 5 /* e32 */, 0 /* tu, mu */
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
     ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vmv0 = COPY $v8
-    ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_V_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
+    ; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY1]], [[COPY1]], killed [[COPY2]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
     %0:vr = COPY $v8
     %2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
     %3:vrnov0 = PseudoVMV_V_V_MF2 %0, killed %2, 0, 5 /* e32 */, 0 /* tu, mu */