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Simplify handling of value types
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llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22219,11 +22219,11 @@ static SDValue performExtendCombine(SDNode *N,
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// ...)), which is what this pattern would otherwise be lowered to.
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if (N->getOpcode() == ISD::ANY_EXTEND &&
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N->getOperand(0).getOpcode() == ISD::BSWAP &&
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N->getOperand(0).getValueType().isScalarInteger() &&
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N->getOperand(0).getValueType().getFixedSizeInBits() == 16) {
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N->getOperand(0).getValueType() == MVT::i16) {
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SDNode *BswapNode = N->getOperand(0).getNode();
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SDValue NewAnyExtend = DAG.getNode(ISD::ANY_EXTEND, SDLoc(BswapNode),
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EVT(MVT::i32), BswapNode->getOperand(0));
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SDValue NewAnyExtend =
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DAG.getNode(ISD::ANY_EXTEND, SDLoc(BswapNode), N->getValueType(0),
22226+
BswapNode->getOperand(0));
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return DAG.getNode(AArch64ISD::REV16, SDLoc(N), N->getValueType(0),
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NewAnyExtend);
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}

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