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[EarlyIfCvt] Don't if-convert if condition has only loop-invariant ops.
This patch adds a heuristic to skip if-conversion if the condition has a high chance of being predictable. If the condition is in a loop, consider it predictable if the condition itself or all its operands are loop-invariant. E.g. this considers a load from a loop-invariant address predictable; we were unable to prove that it doesn't alias any of the memory-writes in the loop, but it is likely to read to same value multiple times. This is a relatively crude heuristic, but it helps to prevent excessive if-conversion in multiple workloads in practice. Reviewed By: apostolakis Differential Revision: https://reviews.llvm.org/D141639
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-19
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2 files changed

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‎llvm/lib/CodeGen/EarlyIfConversion.cpp

Lines changed: 33 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,10 +119,10 @@ class SSAIfConv {
119119

120120
SmallVector<PHIInfo, 8> PHIs;
121121

122-
private:
123122
/// The branch condition determined by analyzeBranch.
124123
SmallVector<MachineOperand, 4> Cond;
125124

125+
private:
126126
/// Instructions in Head that define values used by the conditional blocks.
127127
/// The hoisted instructions must be inserted after these instructions.
128128
SmallPtrSet<MachineInstr*, 8> InsertAfter;
@@ -876,6 +876,38 @@ bool EarlyIfConverter::shouldConvertIf() {
876876
if (Stress)
877877
return true;
878878

879+
// Do not try to if-convert if the condition has a high chance of being
880+
// predictable.
881+
MachineLoop *CurrentLoop = Loops->getLoopFor(IfConv.Head);
882+
// If the condition is in a loop, consider it predictable if the condition
883+
// itself or all its operands are loop-invariant. E.g. this considers a load
884+
// from a loop-invariant address predictable; we were unable to prove that it
885+
// doesn't alias any of the memory-writes in the loop, but it is likely to
886+
// read to same value multiple times.
887+
if (CurrentLoop && any_of(IfConv.Cond, [&](MachineOperand &MO) {
888+
if (!MO.isReg() || !MO.isUse())
889+
return false;
890+
Register Reg = MO.getReg();
891+
if (Register::isPhysicalRegister(Reg))
892+
return false;
893+
894+
MachineInstr *Def = MRI->getVRegDef(Reg);
895+
return CurrentLoop->isLoopInvariant(*Def) ||
896+
all_of(Def->operands(), [&](MachineOperand &Op) {
897+
if (Op.isImm())
898+
return true;
899+
if (!MO.isReg() || !MO.isUse())
900+
return false;
901+
Register Reg = MO.getReg();
902+
if (Register::isPhysicalRegister(Reg))
903+
return false;
904+
905+
MachineInstr *Def = MRI->getVRegDef(Reg);
906+
return CurrentLoop->isLoopInvariant(*Def);
907+
});
908+
}))
909+
return false;
910+
879911
if (!MinInstr)
880912
MinInstr = Traces->getEnsemble(MachineTraceStrategy::TS_MinInstrCount);
881913

‎llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir

Lines changed: 35 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -33,27 +33,35 @@ body: |
3333
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
3434
; CHECK-NEXT: {{ $}}
3535
; CHECK-NEXT: bb.1:
36-
; CHECK-NEXT: successors: %bb.1(0x80000000)
36+
; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.2(0x50000000)
3737
; CHECK-NEXT: {{ $}}
38-
; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32common = LDRBBui [[COPY3]], 0 :: (load (s8))
38+
; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY3]], 0 :: (load (s8))
3939
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
40-
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[COPY4]]
40+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[COPY4]]
41+
; CHECK-NEXT: CBZW killed [[LDRBBui]], %bb.3
42+
; CHECK-NEXT: B %bb.2
43+
; CHECK-NEXT: {{ $}}
44+
; CHECK-NEXT: bb.2:
45+
; CHECK-NEXT: successors: %bb.3(0x80000000)
46+
; CHECK-NEXT: {{ $}}
4147
; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 4080, 12, implicit-def $nzcv
4248
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16711680
4349
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32common = CSELWr [[COPY1]], killed [[MOVi32imm]], 11, implicit $nzcv
4450
; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[CSELWr]], 0, 0, implicit-def $nzcv
4551
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32 = COPY $wzr
4652
; CHECK-NEXT: [[CSELWr1:%[0-9]+]]:gpr32 = CSELWr [[CSELWr]], [[COPY6]], 12, implicit $nzcv
47-
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32 = COPY [[CSELWr1]]
53+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32all = COPY [[CSELWr1]]
4854
; CHECK-NEXT: [[SUBSWri2:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 0, 0, implicit-def $nzcv
4955
; CHECK-NEXT: [[CSELWr2:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[COPY6]], 12, implicit $nzcv
50-
; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr32 = COPY [[CSELWr2]]
51-
; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
52-
; CHECK-NEXT: [[CSELWr3:%[0-9]+]]:gpr32 = CSELWr [[COPY5]], [[COPY7]], 0, implicit $nzcv
53-
; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
54-
; CHECK-NEXT: [[CSELWr4:%[0-9]+]]:gpr32 = CSELWr [[COPY5]], [[COPY8]], 0, implicit $nzcv
55-
; CHECK-NEXT: STRBBui [[CSELWr4]], [[COPY2]], 0 :: (store (s8))
56-
; CHECK-NEXT: STRBBui [[CSELWr3]], [[COPY]], 0 :: (store (s8))
56+
; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr32all = COPY [[CSELWr2]]
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: bb.3:
59+
; CHECK-NEXT: successors: %bb.1(0x80000000)
60+
; CHECK-NEXT: {{ $}}
61+
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY5]], %bb.1, [[COPY7]], %bb.2
62+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr32 = PHI [[COPY5]], %bb.1, [[COPY8]], %bb.2
63+
; CHECK-NEXT: STRBBui [[PHI1]], [[COPY2]], 0 :: (store (s8))
64+
; CHECK-NEXT: STRBBui [[PHI]], [[COPY]], 0 :: (store (s8))
5765
; CHECK-NEXT: B %bb.1
5866
bb.0:
5967
liveins: $x0, $x1, $w2, $x3
@@ -108,17 +116,26 @@ body: |
108116
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
109117
; CHECK-NEXT: {{ $}}
110118
; CHECK-NEXT: bb.1:
111-
; CHECK-NEXT: successors: %bb.1(0x80000000)
119+
; CHECK-NEXT: successors: %bb.3(0x30000000), %bb.2(0x50000000)
112120
; CHECK-NEXT: {{ $}}
113-
; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32common = LDRBBui [[COPY3]], 0 :: (load (s8))
121+
; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY3]], 0 :: (load (s8))
114122
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
115123
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[COPY4]]
116-
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32 = COPY [[LDRBBui]]
124+
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
125+
; CHECK-NEXT: CBZW killed [[LDRBBui]], %bb.3
126+
; CHECK-NEXT: B %bb.2
127+
; CHECK-NEXT: {{ $}}
128+
; CHECK-NEXT: bb.2:
129+
; CHECK-NEXT: successors: %bb.3(0x80000000)
130+
; CHECK-NEXT: {{ $}}
117131
; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 4080, 12, implicit-def $nzcv
118-
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32 = COPY [[SUBSWri]]
119-
; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
120-
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY6]], [[COPY7]], 0, implicit $nzcv
121-
; CHECK-NEXT: STRBBui [[CSELWr]], [[COPY]], 0 :: (store (s8))
132+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32all = COPY [[SUBSWri]]
133+
; CHECK-NEXT: {{ $}}
134+
; CHECK-NEXT: bb.3:
135+
; CHECK-NEXT: successors: %bb.1(0x80000000)
136+
; CHECK-NEXT: {{ $}}
137+
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY6]], %bb.1, [[COPY7]], %bb.2
138+
; CHECK-NEXT: STRBBui [[PHI]], [[COPY]], 0 :: (store (s8))
122139
; CHECK-NEXT: B %bb.1
123140
bb.0:
124141
liveins: $x0, $x1, $w2, $x3

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