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Add testcases.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -288,3 +288,64 @@ define <8 x half> @test_vp_splice_v8f16_masked(<8 x half> %va, <8 x half> %vb, <
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%v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
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ret <8 x half> %v
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}
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define <4 x i32> @test_vp_splice_v4i32_with_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_v4i32_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v9, a0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <4 x i32> poison, i32 %first, i32 0
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%v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
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ret <4 x i32> %v
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}
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define <4 x i32> @test_vp_splice_v4i32_with_splat_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_v4i32_with_splat_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%ins = insertelement <4 x i32> poison, i32 %first, i32 0
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%splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer
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%v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %splat, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
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ret <4 x i32> %v
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}
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define <4 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <4 x float> poison, float %first, i32 0
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%v = call <4 x float> @llvm.experimental.vp.splice.nxv2f32(<4 x float> %va, <4 x float> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
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ret <4 x float> %v
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}
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define <4 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <4 x half> %vb, <4 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2f16_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <4 x half> poison, half %first, i32 0
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%v = call <4 x half> @llvm.experimental.vp.splice.nxv2f16(<4 x half> %va, <4 x half> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
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ret <4 x half> %v
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}

‎llvm/test/CodeGen/RISCV/rvv/vp-splice.ll

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v -verify-machineinstrs \
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; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfh -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
44

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declare <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32, <vscale x 2 x i1>, i32, i32)
@@ -427,3 +427,64 @@ define <vscale x 16 x i64> @test_vp_splice_nxv16i64_negative_offset(<vscale x 16
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%v = call <vscale x 16 x i64> @llvm.experimental.vp.splice.nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 -1, <vscale x 16 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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ret <vscale x 16 x i64> %v
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}
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define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v9, a0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
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%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
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ret <vscale x 2 x i32> %v
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}
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define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2i32_with_splat_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%ins = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
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%splat = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %splat, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
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ret <vscale x 2 x i32> %v
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}
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define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <vscale x 2 x float> poison, float %first, i32 0
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%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
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ret <vscale x 2 x float> %v
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}
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define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_splice_nxv2f16_with_firstelt:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vslidedown.vi v9, v9, 0, v0.t
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
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; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%va = insertelement <vscale x 2 x half> poison, half %first, i32 0
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%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
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ret <vscale x 2 x half> %v
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}

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