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VyacheslavLevytskyyVyacheslavLevytskyy
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experiment with cashes
1 parent bbbb8fa commit e3e508f

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5 files changed

+65
-77
lines changed

5 files changed

+65
-77
lines changed

‎llvm/lib/Target/SPIRV/SPIRVIRMapping.h

Lines changed: 45 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626

2727
namespace llvm {
2828
namespace SPIRV {
29-
29+
/*
3030
inline size_t to_hash(const MachineInstr *MI,
3131
std::unordered_set<const MachineInstr *> &Visited) {
3232
if (!MI || !Visited.insert(MI).second)
@@ -47,6 +47,21 @@ inline size_t to_hash(const MachineInstr *MI) {
4747
std::unordered_set<const MachineInstr *> Visited;
4848
return to_hash(MI, Visited);
4949
}
50+
*/
51+
52+
inline size_t to_hash(const MachineInstr *MI) {
53+
hash_code H = llvm::hash_combine(MI->getOpcode(), MI->getNumOperands());
54+
for (unsigned I = MI->getNumDefs(); I < MI->getNumOperands(); ++I) {
55+
const MachineOperand &MO = MI->getOperand(I);
56+
if (MO.getType() == MachineOperand::MO_CImmediate)
57+
H = llvm::hash_combine(H, MO.getType(), MO.getCImm());
58+
else if (MO.getType() == MachineOperand::MO_FPImmediate)
59+
H = llvm::hash_combine(H, MO.getType(), MO.getFPImm());
60+
else
61+
H = llvm::hash_combine(H, MO.getType());
62+
}
63+
return H;
64+
}
5065

5166
using MIHandle = std::pair<const MachineInstr *, size_t>;
5267

@@ -169,46 +184,54 @@ inline IRHandle handle(const MachineInstr *KeyMI) {
169184
// per an LLVM/GlobalISel entity (e.g., Type, Constant, Machine Instruction).
170185
class SPIRVIRMapping {
171186
DenseMap<SPIRV::IRHandleMF, SPIRV::MIHandle> Vregs;
172-
DenseMap<SPIRV::MIHandle, SPIRV::IRHandle> Defs;
187+
DenseMap<const MachineInstr *, SPIRV::IRHandleMF> Defs;
173188

174189
public:
175190
bool add(SPIRV::IRHandle Handle, const MachineInstr *MI) {
176-
if (std::get<1>(Handle) == 17 && std::get<2>(Handle) == 8) {
177-
const Value *Ptr = (const Value *)std::get<0>(Handle);
178-
if (const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(Ptr)) {
179-
if (CI->getZExtValue() == 8 || CI->getZExtValue() == 5) {
180-
[[maybe_unused]] uint64_t v = CI->getZExtValue();
181-
}
182-
}
191+
if (auto DefIt = Defs.find(MI); DefIt != Defs.end()) {
192+
auto [ExistHandle, ExistMF] = DefIt->second;
193+
if (Handle == ExistHandle && MI->getMF() == ExistMF)
194+
return false; // already exists
195+
// invalidate the record
196+
Vregs.erase(DefIt->second);
197+
Defs.erase(DefIt);
183198
}
184-
auto MIKey = SPIRV::getMIKey(MI);
185-
auto [It, Inserted] =
186-
Vregs.try_emplace(std::make_pair(Handle, MI->getMF()), MIKey);
187-
if (Inserted) {
188-
[[maybe_unused]] auto [_, IsConsistent] =
189-
Defs.insert_or_assign(MIKey, Handle);
190-
assert(IsConsistent);
199+
SPIRV::IRHandleMF HandleMF = SPIRV::getIRHandleMF(Handle, MI->getMF());
200+
SPIRV::MIHandle MIKey = SPIRV::getMIKey(MI);
201+
auto It1 = Vregs.try_emplace(HandleMF, MIKey);
202+
if (!It1.second) {
203+
// there is an expired record
204+
auto [ExistMI, _] = It1.first->second;
205+
// invalidate the record
206+
Defs.erase(ExistMI);
207+
// update the record
208+
It1.first->second = MIKey;
191209
}
192-
return Inserted;
210+
[[maybe_unused]] auto It2 = Defs.try_emplace(MI, HandleMF);
211+
assert(It2.second);
212+
return true;
193213
}
194214
bool erase(const MachineInstr *MI) {
195215
bool Res = false;
196-
if (auto It = Defs.find(SPIRV::getMIKey(MI)); It != Defs.end()) {
197-
Res = Vregs.erase(SPIRV::getIRHandleMF(It->second, MI->getMF()));
216+
if (auto It = Defs.find(MI); It != Defs.end()) {
217+
Res = Vregs.erase(It->second);
198218
Defs.erase(It);
199219
}
200220
return Res;
201221
}
202222
const MachineInstr *findMI(SPIRV::IRHandle Handle,
203223
const MachineFunction *MF) {
204-
auto It = Vregs.find(SPIRV::getIRHandleMF(Handle, MF));
224+
SPIRV::IRHandleMF HandleMF = SPIRV::getIRHandleMF(Handle, MF);
225+
auto It = Vregs.find(HandleMF);
205226
if (It == Vregs.end())
206227
return nullptr;
207228
auto [MI, Hash] = It->second;
208-
if (SPIRV::to_hash(MI) != Hash) {
229+
assert(SPIRV::to_hash(MI) == Hash);
230+
assert(Defs.find(MI) != Defs.end() && Defs.find(MI)->second == HandleMF);
231+
/*if (SPIRV::to_hash(MI) != Hash) {
209232
erase(MI);
210233
return nullptr;
211-
}
234+
}*/
212235
return MI;
213236
}
214237
Register find(SPIRV::IRHandle Handle, const MachineFunction *MF) {

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,6 @@ include "SPIRVSymbolicOperands.td"
1515

1616
// Codegen only metadata instructions
1717
let isCodeGenOnly=1 in {
18-
def TYPEREF: Pseudo<(outs), (ins ID:$src_id, TYPE:$src_ty)>;
1918
def ASSIGN_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
2019
def DECL_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
2120
def GET_ID: Pseudo<(outs iID:$dst_id), (ins iID:$src)>;
@@ -29,10 +28,8 @@ let isCodeGenOnly=1 in {
2928
def SPVTypeBin : SDTypeProfile<1, 2, []>;
3029

3130
def assigntype : SDNode<"SPIRVISD::AssignType", SPVTypeBin>;
32-
def typeref : SDNode<"SPIRVISD::TypeRef", SPVTypeBin>;
3331

3432
def : GINodeEquiv<ASSIGN_TYPE, assigntype>;
35-
def : GINodeEquiv<TYPEREF, typeref>;
3633

3734
class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
3835
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, ID:$src, ID:$src2),

‎llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Lines changed: 15 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -393,26 +393,21 @@ void SPIRVInstructionSelector::resetVRegsType(MachineFunction &MF) {
393393
}
394394
for (const auto &MBB : MF) {
395395
for (const auto &MI : MBB) {
396-
if (MI.getOpcode() == SPIRV::ASSIGN_TYPE) {
397-
Register DstReg = MI.getOperand(0).getReg();
398-
LLT DstType = MRI.getType(DstReg);
399-
Register SrcReg = MI.getOperand(1).getReg();
400-
LLT SrcType = MRI.getType(SrcReg);
401-
if (DstType != SrcType)
402-
MRI.setType(DstReg, MRI.getType(SrcReg));
403-
404-
const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
405-
const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
406-
if (DstRC != SrcRC && SrcRC)
407-
MRI.setRegClass(DstReg, SrcRC);
408-
} else if (MI.getOpcode() == SPIRV::TYPEREF) {
409-
Register DstReg = MI.getOperand(0).getReg();
410-
LLT DstType = MRI.getType(DstReg);
411-
Register SrcReg = MI.getOperand(1).getReg();
412-
LLT SrcType = MRI.getType(SrcReg);
413-
if (DstType != SrcType)
414-
MRI.setType(DstReg, MRI.getType(SrcReg));
415-
}
396+
//GR.invalidateMachineInstr(&I);
397+
if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
398+
continue;
399+
400+
Register DstReg = MI.getOperand(0).getReg();
401+
LLT DstType = MRI.getType(DstReg);
402+
Register SrcReg = MI.getOperand(1).getReg();
403+
LLT SrcType = MRI.getType(SrcReg);
404+
if (DstType != SrcType)
405+
MRI.setType(DstReg, MRI.getType(SrcReg));
406+
407+
const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
408+
const TargetRegisterClass *SrcRC = MRI.getRegClassOrNull(SrcReg);
409+
if (DstRC != SrcRC && SrcRC)
410+
MRI.setRegClass(DstReg, SrcRC);
416411
}
417412
}
418413
}
@@ -523,27 +518,6 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
523518
GR.invalidateMachineInstr(&I);
524519
I.removeFromParent();
525520
return true;
526-
} else if (Opcode == SPIRV::TYPEREF) {
527-
Register SrcReg = I.getOperand(0).getReg();
528-
auto *Def = MRI->getVRegDef(SrcReg);
529-
if (isTypeFoldingSupported(Def->getOpcode())) {
530-
bool Res = selectImpl(I, *CoverageInfo);
531-
LLVM_DEBUG({
532-
if (!Res && Def->getOpcode() != TargetOpcode::G_CONSTANT) {
533-
dbgs() << "Unexpected pattern in ASSIGN_TYPE.\nInstruction: ";
534-
I.print(dbgs());
535-
}
536-
});
537-
assert(Res || Def->getOpcode() == TargetOpcode::G_CONSTANT);
538-
if (Res) {
539-
if (!isTriviallyDead(*Def, *MRI) && isDead(*Def, *MRI))
540-
DeadMIs.insert(Def);
541-
return Res;
542-
}
543-
}
544-
GR.invalidateMachineInstr(&I);
545-
I.removeFromParent();
546-
return true;
547521
} else if (I.getNumDefs() == 1) {
548522
// Make all vregs 64 bits (for SPIR-V IDs).
549523
MRI->setType(I.getOperand(0).getReg(), LLT::scalar(64));

‎llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -564,8 +564,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
564564
assert(Def && "Expecting an instruction that defines the register");
565565
// G_GLOBAL_VALUE already has type info.
566566
if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
567-
Def->getOpcode() != SPIRV::ASSIGN_TYPE &&
568-
Def->getOpcode() != SPIRV::TYPEREF)
567+
Def->getOpcode() != SPIRV::ASSIGN_TYPE)
569568
insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB,
570569
MF.getRegInfo());
571570
ToErase.push_back(&MI);
@@ -576,8 +575,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
576575
assert(Def && "Expecting an instruction that defines the register");
577576
// G_GLOBAL_VALUE already has type info.
578577
if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
579-
Def->getOpcode() != SPIRV::ASSIGN_TYPE &&
580-
Def->getOpcode() != SPIRV::TYPEREF)
578+
Def->getOpcode() != SPIRV::ASSIGN_TYPE)
581579
insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
582580
ToErase.push_back(&MI);
583581
} else if (MIOp == TargetOpcode::FAKE_USE && MI.getNumOperands() > 0) {
@@ -614,8 +612,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
614612
if (isSpvIntrinsic(UseMI, Intrinsic::spv_assign_type) ||
615613
isSpvIntrinsic(UseMI, Intrinsic::spv_assign_name))
616614
continue;
617-
if (UseMI.getOpcode() == SPIRV::ASSIGN_TYPE ||
618-
UseMI.getOpcode() == SPIRV::TYPEREF)
615+
if (UseMI.getOpcode() == SPIRV::ASSIGN_TYPE)
619616
NeedAssignType = false;
620617
}
621618
Type *Ty = nullptr;
@@ -665,9 +662,7 @@ generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
665662
if (!ElemTy) {
666663
// There may be a case when we already know Reg's type.
667664
MachineInstr *NextMI = MI.getNextNode();
668-
if (!NextMI ||
669-
(NextMI->getOpcode() != SPIRV::ASSIGN_TYPE &&
670-
NextMI->getOpcode() != SPIRV::TYPEREF) ||
665+
if (!NextMI || NextMI->getOpcode() != SPIRV::ASSIGN_TYPE ||
671666
NextMI->getOperand(1).getReg() != Reg)
672667
llvm_unreachable("Unexpected opcode");
673668
}

‎llvm/lib/Target/SPIRV/SPIRVUtils.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -186,8 +186,7 @@ MachineBasicBlock::iterator getOpVariableMBBIt(MachineInstr &I) {
186186
if (Opcode == SPIRV::OpFunction || Opcode == SPIRV::OpFunctionParameter) {
187187
IsHeader = true;
188188
} else if (IsHeader &&
189-
!(Opcode == SPIRV::ASSIGN_TYPE || Opcode == SPIRV::TYPEREF ||
190-
Opcode == SPIRV::OpLabel)) {
189+
!(Opcode == SPIRV::ASSIGN_TYPE || Opcode == SPIRV::OpLabel)) {
191190
++It;
192191
break;
193192
}

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