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getVOP3DPPSrcForVT
!cond
1 parent 5c57fd7 commit e3f88a9Copy full SHA for e3f88a9
llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1571,13 +1571,15 @@ class getVOP3SrcForVT<ValueType VT, bit IsTrue16 = 0> {
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// Src2 of VOP3 DPP instructions cannot be a literal
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class getVOP3DPPSrcForVT<ValueType VT> {
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RegisterOperand ret =
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- !if (!eq(VT.Value, i1.Value), SSrc_i1,
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- !if (VT.isFP,
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- !if (!or(!eq(VT.Value, f16.Value), !eq(VT.Value, bf16.Value)), VCSrc_f16,
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- !if (!or(!eq(VT.Value, v2f16.Value), !eq(VT.Value, v2bf16.Value)), VCSrc_v2f16, VCSrc_f32)),
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- !if (!eq(VT.Value, i16.Value), VCSrc_b16,
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- !if (!eq(VT.Value, v2i16.Value), VCSrc_v2b16,
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- VCSrc_b32))));
+ !cond(!eq(VT, i1) : SSrc_i1,
+ !eq(VT, i16) : VCSrc_b16,
+ !eq(VT, f16) : VCSrc_f16,
+ !eq(VT, bf16) : VCSrc_f16,
+ !eq(VT, v2i16) : VCSrc_v2b16,
+ !eq(VT, v2f16) : VCSrc_v2f16,
+ !eq(VT, v2bf16) : VCSrc_v2f16,
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+ !eq(VT, f32) : VCSrc_f32,
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+ 1 : VCSrc_b32);
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}
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// Float or packed int
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