Skip to content

Commit e44a305

Browse files
rotaterightrotateright
committed
[InstCombine] invert canonicalization of sext (x > -1) --> not (ashr x)
https://alive2.llvm.org/ce/z/2iC4oB This is similar to changes made for zext + lshr: 21d3871 6c39a3a The existing fold did not account for extra uses, so we see some instruction count reductions in the test diffs. This is intended to improve analysis (icmp likely has more transforms than any other opcode), make other transforms more symmetric with zext/lshr, and it can be inverted in codegen if profitable. As with the earlier changes, there is potential to uncover infinite combine loops, but I have not found any yet.
1 parent 7ea998e commit e44a305

File tree

11 files changed

+54
-58
lines changed

11 files changed

+54
-58
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3896,6 +3896,14 @@ Instruction *InstCombinerImpl::foldNot(BinaryOperator &I) {
38963896
if (match(NotVal, m_AShr(m_Not(m_Value(X)), m_Value(Y))))
38973897
return BinaryOperator::CreateAShr(X, Y);
38983898

3899+
// Bit-hack form of a signbit test:
3900+
// iN ~X >>s (N-1) --> sext i1 (X > -1) to iN
3901+
unsigned FullShift = Ty->getScalarSizeInBits() - 1;
3902+
if (match(NotVal, m_OneUse(m_AShr(m_Value(X), m_SpecificInt(FullShift))))) {
3903+
Value *IsNotNeg = Builder.CreateIsNotNeg(X, "isnotneg");
3904+
return new SExtInst(IsNotNeg, Ty);
3905+
}
3906+
38993907
// If we are inverting a right-shifted constant, we may be able to eliminate
39003908
// the 'not' by inverting the constant and using the opposite shift type.
39013909
// Canonicalization rules ensure that only a negative constant uses 'ashr',

‎llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1368,18 +1368,14 @@ Instruction *InstCombinerImpl::transformSExtICmp(ICmpInst *Cmp,
13681368
if (!Op1->getType()->isIntOrIntVectorTy())
13691369
return nullptr;
13701370

1371-
if ((Pred == ICmpInst::ICMP_SLT && match(Op1, m_ZeroInt())) ||
1372-
(Pred == ICmpInst::ICMP_SGT && match(Op1, m_AllOnes()))) {
1373-
// (x <s 0) ? -1 : 0 -> ashr x, 31 -> all ones if negative
1374-
// (x >s -1) ? -1 : 0 -> not (ashr x, 31) -> all ones if positive
1371+
if (Pred == ICmpInst::ICMP_SLT && match(Op1, m_ZeroInt())) {
1372+
// sext (x <s 0) --> ashr x, 31 (all ones if negative)
13751373
Value *Sh = ConstantInt::get(Op0->getType(),
13761374
Op0->getType()->getScalarSizeInBits() - 1);
13771375
Value *In = Builder.CreateAShr(Op0, Sh, Op0->getName() + ".lobit");
13781376
if (In->getType() != Sext.getType())
13791377
In = Builder.CreateIntCast(In, Sext.getType(), true /*SExt*/);
13801378

1381-
if (Pred == ICmpInst::ICMP_SGT)
1382-
In = Builder.CreateNot(In, In->getName() + ".not");
13831379
return replaceInstUsesWith(Sext, In);
13841380
}
13851381

‎llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -158,9 +158,8 @@ define <4 x i64> @mload_v4i64(ptr %f) {
158158

159159
define <4 x i64> @mload_v4i64_cmp(ptr %f, <4 x i64> %src) {
160160
; CHECK-LABEL: @mload_v4i64_cmp(
161-
; CHECK-NEXT: [[SRC_LOBIT:%.*]] = ashr <4 x i64> [[SRC:%.*]], <i64 63, i64 63, i64 63, i64 63>
162-
; CHECK-NEXT: [[SRC_LOBIT_NOT:%.*]] = xor <4 x i64> [[SRC_LOBIT]], <i64 -1, i64 -1, i64 -1, i64 -1>
163-
; CHECK-NEXT: [[LD:%.*]] = tail call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr [[F:%.*]], <4 x i64> [[SRC_LOBIT_NOT]])
161+
; CHECK-NEXT: [[ICMP:%.*]] = icmp sgt <4 x i64> [[SRC:%.*]], <i64 -1, i64 -1, i64 -1, i64 -1>
162+
; CHECK-NEXT: [[LD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[F:%.*]], i32 1, <4 x i1> [[ICMP]], <4 x i64> zeroinitializer)
164163
; CHECK-NEXT: ret <4 x i64> [[LD]]
165164
;
166165
%icmp = icmp sge <4 x i64> %src, zeroinitializer
@@ -271,10 +270,8 @@ define void @mstore_v4f64(ptr %f, <4 x double> %v) {
271270

272271
define void @mstore_v4f64_cmp(ptr %f, <4 x i32> %src, <4 x double> %v) {
273272
; CHECK-LABEL: @mstore_v4f64_cmp(
274-
; CHECK-NEXT: [[SRC_LOBIT:%.*]] = ashr <4 x i32> [[SRC:%.*]], <i32 31, i32 31, i32 31, i32 31>
275-
; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i32> [[SRC_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
276-
; CHECK-NEXT: [[DOTNOT:%.*]] = sext <4 x i32> [[TMP1]] to <4 x i64>
277-
; CHECK-NEXT: tail call void @llvm.x86.avx.maskstore.pd.256(ptr [[F:%.*]], <4 x i64> [[DOTNOT]], <4 x double> [[V:%.*]])
273+
; CHECK-NEXT: [[ICMP:%.*]] = icmp sgt <4 x i32> [[SRC:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
274+
; CHECK-NEXT: call void @llvm.masked.store.v4f64.p0(<4 x double> [[V:%.*]], ptr [[F:%.*]], i32 1, <4 x i1> [[ICMP]])
278275
; CHECK-NEXT: ret void
279276
;
280277
%icmp = icmp sge <4 x i32> %src, zeroinitializer

‎llvm/test/Transforms/InstCombine/and.ll

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1770,8 +1770,8 @@ define i16 @not_signbit_splat_mask2(i8 %x, i16 %y) {
17701770

17711771
define i8 @not_ashr_bitwidth_mask(i8 %x, i8 %y) {
17721772
; CHECK-LABEL: @not_ashr_bitwidth_mask(
1773-
; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i8 [[X:%.*]], 0
1774-
; CHECK-NEXT: [[POS_OR_ZERO:%.*]] = select i1 [[ISNEG]], i8 0, i8 [[Y:%.*]]
1773+
; CHECK-NEXT: [[ISNOTNEG_INV:%.*]] = icmp slt i8 [[X:%.*]], 0
1774+
; CHECK-NEXT: [[POS_OR_ZERO:%.*]] = select i1 [[ISNOTNEG_INV]], i8 0, i8 [[Y:%.*]]
17751775
; CHECK-NEXT: ret i8 [[POS_OR_ZERO]]
17761776
;
17771777
%sign = ashr i8 %x, 7
@@ -1783,8 +1783,8 @@ define i8 @not_ashr_bitwidth_mask(i8 %x, i8 %y) {
17831783
define <2 x i8> @not_ashr_bitwidth_mask_vec_commute(<2 x i8> %x, <2 x i8> %py) {
17841784
; CHECK-LABEL: @not_ashr_bitwidth_mask_vec_commute(
17851785
; CHECK-NEXT: [[Y:%.*]] = mul <2 x i8> [[PY:%.*]], <i8 42, i8 2>
1786-
; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
1787-
; CHECK-NEXT: [[POS_OR_ZERO:%.*]] = select <2 x i1> [[ISNEG]], <2 x i8> zeroinitializer, <2 x i8> [[Y]]
1786+
; CHECK-NEXT: [[ISNOTNEG_INV:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
1787+
; CHECK-NEXT: [[POS_OR_ZERO:%.*]] = select <2 x i1> [[ISNOTNEG_INV]], <2 x i8> zeroinitializer, <2 x i8> [[Y]]
17881788
; CHECK-NEXT: ret <2 x i8> [[POS_OR_ZERO]]
17891789
;
17901790
%y = mul <2 x i8> %py, <i8 42, i8 2> ; thwart complexity-based ordering
@@ -1815,8 +1815,8 @@ define i8 @not_ashr_bitwidth_mask_use1(i8 %x, i8 %y) {
18151815

18161816
define i8 @not_ashr_bitwidth_mask_use2(i8 %x, i8 %y) {
18171817
; CHECK-LABEL: @not_ashr_bitwidth_mask_use2(
1818-
; CHECK-NEXT: [[SIGN:%.*]] = ashr i8 [[X:%.*]], 7
1819-
; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[SIGN]], -1
1818+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1
1819+
; CHECK-NEXT: [[NOT:%.*]] = sext i1 [[ISNOTNEG]] to i8
18201820
; CHECK-NEXT: call void @use8(i8 [[NOT]])
18211821
; CHECK-NEXT: [[R:%.*]] = and i8 [[NOT]], [[Y:%.*]]
18221822
; CHECK-NEXT: ret i8 [[R]]
@@ -1860,8 +1860,8 @@ define i8 @not_lshr_bitwidth_mask(i8 %x, i8 %y) {
18601860

18611861
define i16 @invert_signbit_splat_mask(i8 %x, i16 %y) {
18621862
; CHECK-LABEL: @invert_signbit_splat_mask(
1863-
; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i8 [[X:%.*]], 0
1864-
; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNEG]], i16 0, i16 [[Y:%.*]]
1863+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1
1864+
; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNOTNEG]], i16 [[Y:%.*]], i16 0
18651865
; CHECK-NEXT: ret i16 [[R]]
18661866
;
18671867
%a = ashr i8 %x, 7
@@ -1904,11 +1904,10 @@ define i16 @invert_signbit_splat_mask_use1(i8 %x, i16 %y) {
19041904

19051905
define i16 @invert_signbit_splat_mask_use2(i8 %x, i16 %y) {
19061906
; CHECK-LABEL: @invert_signbit_splat_mask_use2(
1907-
; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 7
1908-
; CHECK-NEXT: [[N:%.*]] = xor i8 [[A]], -1
1907+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1
1908+
; CHECK-NEXT: [[N:%.*]] = sext i1 [[ISNOTNEG]] to i8
19091909
; CHECK-NEXT: call void @use8(i8 [[N]])
1910-
; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt i8 [[X]], 0
1911-
; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNEG]], i16 0, i16 [[Y:%.*]]
1910+
; CHECK-NEXT: [[R:%.*]] = select i1 [[ISNOTNEG]], i16 [[Y:%.*]], i16 0
19121911
; CHECK-NEXT: ret i16 [[R]]
19131912
;
19141913
%a = ashr i8 %x, 7
@@ -1923,9 +1922,8 @@ define i16 @invert_signbit_splat_mask_use2(i8 %x, i16 %y) {
19231922

19241923
define i16 @invert_signbit_splat_mask_use3(i8 %x, i16 %y) {
19251924
; CHECK-LABEL: @invert_signbit_splat_mask_use3(
1926-
; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 7
1927-
; CHECK-NEXT: [[N:%.*]] = xor i8 [[A]], -1
1928-
; CHECK-NEXT: [[S:%.*]] = sext i8 [[N]] to i16
1925+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1
1926+
; CHECK-NEXT: [[S:%.*]] = sext i1 [[ISNOTNEG]] to i16
19291927
; CHECK-NEXT: call void @use16(i16 [[S]])
19301928
; CHECK-NEXT: [[R:%.*]] = and i16 [[S]], [[Y:%.*]]
19311929
; CHECK-NEXT: ret i16 [[R]]
@@ -1942,8 +1940,8 @@ define i16 @invert_signbit_splat_mask_use3(i8 %x, i16 %y) {
19421940

19431941
define i16 @not_invert_signbit_splat_mask1(i8 %x, i16 %y) {
19441942
; CHECK-LABEL: @not_invert_signbit_splat_mask1(
1945-
; CHECK-NEXT: [[A:%.*]] = ashr i8 [[X:%.*]], 7
1946-
; CHECK-NEXT: [[N:%.*]] = xor i8 [[A]], -1
1943+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1
1944+
; CHECK-NEXT: [[N:%.*]] = sext i1 [[ISNOTNEG]] to i8
19471945
; CHECK-NEXT: [[Z:%.*]] = zext i8 [[N]] to i16
19481946
; CHECK-NEXT: [[R:%.*]] = and i16 [[Z]], [[Y:%.*]]
19491947
; CHECK-NEXT: ret i16 [[R]]

‎llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -75,9 +75,9 @@ define <2 x i32> @or_bitcast_int_to_vec(i64 %a) {
7575

7676
define <2 x i64> @is_negative(<4 x i32> %x) {
7777
; CHECK-LABEL: @is_negative(
78-
; CHECK-NEXT: [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
79-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[LOBIT]] to <2 x i64>
80-
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
78+
; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
79+
; CHECK-NEXT: [[NOTNOT:%.*]] = bitcast <4 x i32> [[X_LOBIT]] to <2 x i64>
80+
; CHECK-NEXT: ret <2 x i64> [[NOTNOT]]
8181
;
8282
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
8383
%not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -91,8 +91,8 @@ define <2 x i64> @is_negative(<4 x i32> %x) {
9191

9292
define <4 x i32> @is_negative_bonus_bitcast(<4 x i32> %x) {
9393
; CHECK-LABEL: @is_negative_bonus_bitcast(
94-
; CHECK-NEXT: [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
95-
; CHECK-NEXT: ret <4 x i32> [[LOBIT]]
94+
; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
95+
; CHECK-NEXT: ret <4 x i32> [[X_LOBIT]]
9696
;
9797
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
9898
%not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>

‎llvm/test/Transforms/InstCombine/bitcast.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -77,9 +77,9 @@ define <2 x i32> @or_bitcast_int_to_vec(i64 %a) {
7777

7878
define <2 x i64> @is_negative(<4 x i32> %x) {
7979
; CHECK-LABEL: @is_negative(
80-
; CHECK-NEXT: [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
81-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[LOBIT]] to <2 x i64>
82-
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
80+
; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
81+
; CHECK-NEXT: [[NOTNOT:%.*]] = bitcast <4 x i32> [[X_LOBIT]] to <2 x i64>
82+
; CHECK-NEXT: ret <2 x i64> [[NOTNOT]]
8383
;
8484
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
8585
%not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -93,8 +93,8 @@ define <2 x i64> @is_negative(<4 x i32> %x) {
9393

9494
define <4 x i32> @is_negative_bonus_bitcast(<4 x i32> %x) {
9595
; CHECK-LABEL: @is_negative_bonus_bitcast(
96-
; CHECK-NEXT: [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
97-
; CHECK-NEXT: ret <4 x i32> [[LOBIT]]
96+
; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
97+
; CHECK-NEXT: ret <4 x i32> [[X_LOBIT]]
9898
;
9999
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
100100
%not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>

‎llvm/test/Transforms/InstCombine/icmp.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -63,9 +63,9 @@ define i32 @test3(i32 %X) {
6363

6464
define i32 @test4(i32 %X) {
6565
; CHECK-LABEL: @test4(
66-
; CHECK-NEXT: [[X_LOBIT:%.*]] = ashr i32 [[X:%.*]], 31
67-
; CHECK-NEXT: [[X_LOBIT_NOT:%.*]] = xor i32 [[X_LOBIT]], -1
68-
; CHECK-NEXT: ret i32 [[X_LOBIT_NOT]]
66+
; CHECK-NEXT: [[A:%.*]] = icmp sgt i32 [[X:%.*]], -1
67+
; CHECK-NEXT: [[B:%.*]] = sext i1 [[A]] to i32
68+
; CHECK-NEXT: ret i32 [[B]]
6969
;
7070
%a = icmp ult i32 %X, -2147483648
7171
%b = sext i1 %a to i32

‎llvm/test/Transforms/InstCombine/overflow-mul.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -215,9 +215,9 @@ define <4 x i32> @pr20113(<4 x i16> %a, <4 x i16> %b) {
215215
; CHECK-NEXT: [[VMOVL_I_I726:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
216216
; CHECK-NEXT: [[VMOVL_I_I712:%.*]] = zext <4 x i16> [[B:%.*]] to <4 x i32>
217217
; CHECK-NEXT: [[MUL_I703:%.*]] = mul nuw <4 x i32> [[VMOVL_I_I712]], [[VMOVL_I_I726]]
218-
; CHECK-NEXT: [[MUL_I703_LOBIT:%.*]] = ashr <4 x i32> [[MUL_I703]], <i32 31, i32 31, i32 31, i32 31>
219-
; CHECK-NEXT: [[MUL_I703_LOBIT_NOT:%.*]] = xor <4 x i32> [[MUL_I703_LOBIT]], <i32 -1, i32 -1, i32 -1, i32 -1>
220-
; CHECK-NEXT: ret <4 x i32> [[MUL_I703_LOBIT_NOT]]
218+
; CHECK-NEXT: [[TMP:%.*]] = icmp sgt <4 x i32> [[MUL_I703]], <i32 -1, i32 -1, i32 -1, i32 -1>
219+
; CHECK-NEXT: [[VCGEZ_I:%.*]] = sext <4 x i1> [[TMP]] to <4 x i32>
220+
; CHECK-NEXT: ret <4 x i32> [[VCGEZ_I]]
221221
;
222222
%vmovl.i.i726 = zext <4 x i16> %a to <4 x i32>
223223
%vmovl.i.i712 = zext <4 x i16> %b to <4 x i32>

‎llvm/test/Transforms/InstCombine/vec_sext.ll

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,8 @@ define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
2626
define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
2727
; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
2828
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
29-
; CHECK-NEXT: [[ISNEG1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
30-
; CHECK-NEXT: [[T2:%.*]] = select <4 x i1> [[ISNEG1]], <4 x i32> [[A]], <4 x i32> zeroinitializer
31-
; CHECK-NEXT: [[ISNEG:%.*]] = icmp slt <4 x i32> [[B]], zeroinitializer
32-
; CHECK-NEXT: [[T3:%.*]] = select <4 x i1> [[ISNEG]], <4 x i32> zeroinitializer, <4 x i32> [[SUB]]
33-
; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
29+
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
30+
; CHECK-NEXT: [[COND:%.*]] = select <4 x i1> [[CMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]]
3431
; CHECK-NEXT: ret <4 x i32> [[COND]]
3532
;
3633
%cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -58,9 +55,9 @@ define <2 x i32> @is_negative_undef_elt(<2 x i32> %a) {
5855

5956
define <2 x i32> @is_positive_undef_elt(<2 x i32> %a) {
6057
; CHECK-LABEL: @is_positive_undef_elt(
61-
; CHECK-NEXT: [[A_LOBIT:%.*]] = ashr <2 x i32> [[A:%.*]], <i32 31, i32 31>
62-
; CHECK-NEXT: [[A_LOBIT_NOT:%.*]] = xor <2 x i32> [[A_LOBIT]], <i32 -1, i32 -1>
63-
; CHECK-NEXT: ret <2 x i32> [[A_LOBIT_NOT]]
58+
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[A:%.*]], <i32 undef, i32 -1>
59+
; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i32>
60+
; CHECK-NEXT: ret <2 x i32> [[SEXT]]
6461
;
6562
%cmp = icmp sgt <2 x i32> %a, <i32 undef, i32 -1>
6663
%sext = sext <2 x i1> %cmp to <2 x i32>

‎llvm/test/Transforms/InstCombine/xor-ashr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,8 +94,8 @@ define i8 @wrongimm(i16 %add) {
9494
define <4 x i32> @vectorpoison(<6 x i32> %0) {
9595
; CHECK-LABEL: @vectorpoison(
9696
; CHECK-NEXT: entry:
97-
; CHECK-NEXT: [[NEG:%.*]] = ashr <6 x i32> [[TMP0:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
98-
; CHECK-NEXT: [[SHR:%.*]] = xor <6 x i32> [[NEG]], <i32 -1, i32 -1, i32 -1, i32 poison, i32 poison, i32 poison>
97+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt <6 x i32> [[TMP0:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
98+
; CHECK-NEXT: [[SHR:%.*]] = sext <6 x i1> [[ISNOTNEG]] to <6 x i32>
9999
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <6 x i32> [[SHR]], <6 x i32> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 2>
100100
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
101101
;

‎llvm/test/Transforms/InstCombine/xor.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1124,8 +1124,8 @@ define i8 @not_ashr(i8 %x) {
11241124

11251125
define <2 x i8> @not_ashr_vec(<2 x i8> %x) {
11261126
; CHECK-LABEL: @not_ashr_vec(
1127-
; CHECK-NEXT: [[A:%.*]] = ashr <2 x i8> [[X:%.*]], <i8 7, i8 7>
1128-
; CHECK-NEXT: [[R:%.*]] = xor <2 x i8> [[A]], <i8 -1, i8 -1>
1127+
; CHECK-NEXT: [[ISNOTNEG:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
1128+
; CHECK-NEXT: [[R:%.*]] = sext <2 x i1> [[ISNOTNEG]] to <2 x i8>
11291129
; CHECK-NEXT: ret <2 x i8> [[R]]
11301130
;
11311131
%a = ashr <2 x i8> %x, <i8 7, i8 7>

0 commit comments

Comments
 (0)