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michaelmaitlandmichaelmaitland
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[RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support (#122353)
We already have getOperandInfo tests that cover this instruction.
1 parent 550d32f commit e44f03d

16 files changed

+1014
-1015
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -551,6 +551,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
551551
case RISCV::VFWCVT_F_XU_V:
552552
case RISCV::VFWCVT_F_X_V:
553553
case RISCV::VFWCVT_F_F_V:
554+
case RISCV::VFWCVTBF16_F_F_V:
554555
return IsMODef ? MILog2SEW + 1 : MILog2SEW;
555556

556557
// Def and Op1 uses EEW=2*SEW. Op2 uses EEW=SEW.
@@ -607,7 +608,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
607608
case RISCV::VFNCVT_F_XU_W:
608609
case RISCV::VFNCVT_F_X_W:
609610
case RISCV::VFNCVT_F_F_W:
610-
case RISCV::VFNCVT_ROD_F_F_W: {
611+
case RISCV::VFNCVT_ROD_F_F_W:
612+
case RISCV::VFNCVTBF16_F_F_W: {
611613
bool IsOp1 = HasPassthru ? MO.getOperandNo() == 2 : MO.getOperandNo() == 1;
612614
bool TwoTimes = IsOp1;
613615
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
@@ -1045,6 +1047,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10451047
case RISCV::VFWCVT_F_XU_V:
10461048
case RISCV::VFWCVT_F_X_V:
10471049
case RISCV::VFWCVT_F_F_V:
1050+
case RISCV::VFWCVTBF16_F_F_V:
10481051
// Narrowing Floating-Point/Integer Type-Convert Instructions
10491052
case RISCV::VFNCVT_XU_F_W:
10501053
case RISCV::VFNCVT_X_F_W:
@@ -1054,6 +1057,7 @@ static bool isSupportedInstr(const MachineInstr &MI) {
10541057
case RISCV::VFNCVT_F_X_W:
10551058
case RISCV::VFNCVT_F_F_W:
10561059
case RISCV::VFNCVT_ROD_F_F_W:
1060+
case RISCV::VFNCVTBF16_F_F_W:
10571061
return true;
10581062
}
10591063

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Lines changed: 14 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,11 @@ define void @fadd_v6bf16(ptr %x, ptr %y) {
3232
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3333
; CHECK-NEXT: vle16.v v8, (a1)
3434
; CHECK-NEXT: vle16.v v9, (a0)
35-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
3635
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
3736
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
3837
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3938
; CHECK-NEXT: vfadd.vv v8, v12, v10
40-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
39+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
4140
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
4241
; CHECK-NEXT: vse16.v v10, (a0)
4342
; CHECK-NEXT: ret
@@ -167,12 +166,11 @@ define void @fsub_v6bf16(ptr %x, ptr %y) {
167166
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
168167
; CHECK-NEXT: vle16.v v8, (a1)
169168
; CHECK-NEXT: vle16.v v9, (a0)
170-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
171169
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
172170
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
173171
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
174172
; CHECK-NEXT: vfsub.vv v8, v12, v10
175-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
173+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
176174
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
177175
; CHECK-NEXT: vse16.v v10, (a0)
178176
; CHECK-NEXT: ret
@@ -302,12 +300,11 @@ define void @fmul_v6bf16(ptr %x, ptr %y) {
302300
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
303301
; CHECK-NEXT: vle16.v v8, (a1)
304302
; CHECK-NEXT: vle16.v v9, (a0)
305-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
306303
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
307304
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
308305
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
309306
; CHECK-NEXT: vfmul.vv v8, v12, v10
310-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
307+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
311308
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
312309
; CHECK-NEXT: vse16.v v10, (a0)
313310
; CHECK-NEXT: ret
@@ -437,12 +434,11 @@ define void @fdiv_v6bf16(ptr %x, ptr %y) {
437434
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
438435
; CHECK-NEXT: vle16.v v8, (a1)
439436
; CHECK-NEXT: vle16.v v9, (a0)
440-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
441437
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
442438
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
443439
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
444440
; CHECK-NEXT: vfdiv.vv v8, v12, v10
445-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
441+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
446442
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
447443
; CHECK-NEXT: vse16.v v10, (a0)
448444
; CHECK-NEXT: ret
@@ -1196,9 +1192,7 @@ define void @copysign_neg_trunc_v3bf16_v3f32(ptr %x, ptr %y) {
11961192
; CHECK-NEXT: lui a1, 8
11971193
; CHECK-NEXT: addi a2, a1, -1
11981194
; CHECK-NEXT: vand.vx v8, v8, a2
1199-
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
12001195
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v9
1201-
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
12021196
; CHECK-NEXT: vxor.vx v9, v10, a1
12031197
; CHECK-NEXT: vand.vx v9, v9, a1
12041198
; CHECK-NEXT: vor.vv v8, v8, v9
@@ -2263,13 +2257,12 @@ define void @fadd_vf_v6bf16(ptr %x, bfloat %y) {
22632257
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
22642258
; CHECK-NEXT: vle16.v v8, (a0)
22652259
; CHECK-NEXT: fmv.x.w a1, fa0
2266-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
22672260
; CHECK-NEXT: vmv.v.x v9, a1
22682261
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
22692262
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
22702263
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
22712264
; CHECK-NEXT: vfadd.vv v8, v10, v12
2272-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2265+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
22732266
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
22742267
; CHECK-NEXT: vse16.v v10, (a0)
22752268
; CHECK-NEXT: ret
@@ -2404,13 +2397,12 @@ define void @fadd_fv_v6bf16(ptr %x, bfloat %y) {
24042397
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
24052398
; CHECK-NEXT: vle16.v v8, (a0)
24062399
; CHECK-NEXT: fmv.x.w a1, fa0
2407-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
24082400
; CHECK-NEXT: vmv.v.x v9, a1
24092401
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
24102402
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
24112403
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
24122404
; CHECK-NEXT: vfadd.vv v8, v12, v10
2413-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2405+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
24142406
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
24152407
; CHECK-NEXT: vse16.v v10, (a0)
24162408
; CHECK-NEXT: ret
@@ -2545,13 +2537,12 @@ define void @fsub_vf_v6bf16(ptr %x, bfloat %y) {
25452537
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
25462538
; CHECK-NEXT: vle16.v v8, (a0)
25472539
; CHECK-NEXT: fmv.x.w a1, fa0
2548-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
25492540
; CHECK-NEXT: vmv.v.x v9, a1
25502541
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
25512542
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
25522543
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
25532544
; CHECK-NEXT: vfsub.vv v8, v10, v12
2554-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2545+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
25552546
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
25562547
; CHECK-NEXT: vse16.v v10, (a0)
25572548
; CHECK-NEXT: ret
@@ -2686,13 +2677,12 @@ define void @fsub_fv_v6bf16(ptr %x, bfloat %y) {
26862677
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
26872678
; CHECK-NEXT: vle16.v v8, (a0)
26882679
; CHECK-NEXT: fmv.x.w a1, fa0
2689-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
26902680
; CHECK-NEXT: vmv.v.x v9, a1
26912681
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
26922682
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
26932683
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
26942684
; CHECK-NEXT: vfsub.vv v8, v12, v10
2695-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2685+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
26962686
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
26972687
; CHECK-NEXT: vse16.v v10, (a0)
26982688
; CHECK-NEXT: ret
@@ -2827,13 +2817,12 @@ define void @fmul_vf_v6bf16(ptr %x, bfloat %y) {
28272817
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
28282818
; CHECK-NEXT: vle16.v v8, (a0)
28292819
; CHECK-NEXT: fmv.x.w a1, fa0
2830-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
28312820
; CHECK-NEXT: vmv.v.x v9, a1
28322821
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
28332822
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
28342823
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
28352824
; CHECK-NEXT: vfmul.vv v8, v10, v12
2836-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2825+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
28372826
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
28382827
; CHECK-NEXT: vse16.v v10, (a0)
28392828
; CHECK-NEXT: ret
@@ -2968,13 +2957,12 @@ define void @fmul_fv_v6bf16(ptr %x, bfloat %y) {
29682957
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
29692958
; CHECK-NEXT: vle16.v v8, (a0)
29702959
; CHECK-NEXT: fmv.x.w a1, fa0
2971-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
29722960
; CHECK-NEXT: vmv.v.x v9, a1
29732961
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
29742962
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
29752963
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
29762964
; CHECK-NEXT: vfmul.vv v8, v12, v10
2977-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
2965+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
29782966
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
29792967
; CHECK-NEXT: vse16.v v10, (a0)
29802968
; CHECK-NEXT: ret
@@ -3109,13 +3097,12 @@ define void @fdiv_vf_v6bf16(ptr %x, bfloat %y) {
31093097
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
31103098
; CHECK-NEXT: vle16.v v8, (a0)
31113099
; CHECK-NEXT: fmv.x.w a1, fa0
3112-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
31133100
; CHECK-NEXT: vmv.v.x v9, a1
31143101
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
31153102
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
31163103
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
31173104
; CHECK-NEXT: vfdiv.vv v8, v10, v12
3118-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3105+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
31193106
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
31203107
; CHECK-NEXT: vse16.v v10, (a0)
31213108
; CHECK-NEXT: ret
@@ -3250,13 +3237,12 @@ define void @fdiv_fv_v6bf16(ptr %x, bfloat %y) {
32503237
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
32513238
; CHECK-NEXT: vle16.v v8, (a0)
32523239
; CHECK-NEXT: fmv.x.w a1, fa0
3253-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
32543240
; CHECK-NEXT: vmv.v.x v9, a1
32553241
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
32563242
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v9
32573243
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
32583244
; CHECK-NEXT: vfdiv.vv v8, v12, v10
3259-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
3245+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
32603246
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
32613247
; CHECK-NEXT: vse16.v v10, (a0)
32623248
; CHECK-NEXT: ret
@@ -4908,7 +4894,6 @@ define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
49084894
; CHECK-NEXT: vle16.v v8, (a1)
49094895
; CHECK-NEXT: vle16.v v9, (a0)
49104896
; CHECK-NEXT: vle16.v v10, (a2)
4911-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
49124897
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
49134898
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
49144899
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
@@ -4919,7 +4904,7 @@ define void @fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
49194904
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
49204905
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
49214906
; CHECK-NEXT: vfadd.vv v8, v8, v12
4922-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
4907+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
49234908
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
49244909
; CHECK-NEXT: vse16.v v10, (a0)
49254910
; CHECK-NEXT: ret
@@ -5082,7 +5067,6 @@ define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
50825067
; CHECK-NEXT: vle16.v v8, (a1)
50835068
; CHECK-NEXT: vle16.v v9, (a0)
50845069
; CHECK-NEXT: vle16.v v10, (a2)
5085-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
50865070
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v8
50875071
; CHECK-NEXT: vfwcvtbf16.f.f.v v14, v9
50885072
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
@@ -5093,7 +5077,7 @@ define void @fmsub_fmuladd_v6bf16(ptr %x, ptr %y, ptr %z) {
50935077
; CHECK-NEXT: vfwcvtbf16.f.f.v v12, v10
50945078
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
50955079
; CHECK-NEXT: vfsub.vv v8, v8, v12
5096-
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5080+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
50975081
; CHECK-NEXT: vfncvtbf16.f.f.w v10, v8
50985082
; CHECK-NEXT: vse16.v v10, (a0)
50995083
; CHECK-NEXT: ret

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