[NFC][AArch64][ARM][Thumb][Hexagon] Autogenerate some tests

These all (and some others) are being affected by D104597,
but they are manually-written, which rather complicates
checking the effect that change has on them.

Author: LebedevRI

llvm/test/CodeGen/AArch64/addsub.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 ; Note that this should be refactored (for efficiency if nothing else)
@@ -11,13 +12,23 @@
 ; Add pure 12-bit immediates:
 define void @add_small() {
 ; CHECK-LABEL: add_small:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, :got:var_i32
+; CHECK-NEXT:    adrp x9, :got:var_i64
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:var_i32]
+; CHECK-NEXT:    ldr x9, [x9, :got_lo12:var_i64]
+; CHECK-NEXT:    ldr w10, [x8]
+; CHECK-NEXT:    ldr x11, [x9]
+; CHECK-NEXT:    add w10, w10, #4095 // =4095
+; CHECK-NEXT:    add x11, x11, #52 // =52
+; CHECK-NEXT:    str w10, [x8]
+; CHECK-NEXT:    str x11, [x9]
+; CHECK-NEXT:    ret
 
-; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52
   %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 52
   store i64 %newval64, i64* @var_i64
@@ -36,33 +47,47 @@ define void @add_small() {
 ; xC = add xA, #12 ; <- xA implicitly zero extend wA.
 define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {
 ; CHECK-LABEL: add_small_imm:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldrb w8, [x0]
+; CHECK-NEXT:    add w9, w8, w2
+; CHECK-NEXT:    add x8, x8, #12 // =12
+; CHECK-NEXT:    str w9, [x3]
+; CHECK-NEXT:    str x8, [x1]
+; CHECK-NEXT:    ret
 entry:
 
-; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0]
   %t = load i8, i8* %p
   %promoted = zext i8 %t to i64
   %zextt = zext i8 %t to i32
   %add = add nuw i32 %zextt, %b
 
-; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12
   %add2 = add nuw i64 %promoted, 12
   store i32 %add, i32* %addr
 
-; CHECK: str [[ADD2]], [x1]
   store i64 %add2, i64* %q
   ret void
 }
 
 ; Add 12-bit immediates, shifted left by 12 bits
 define void @add_med() {
 ; CHECK-LABEL: add_med:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, :got:var_i32
+; CHECK-NEXT:    adrp x9, :got:var_i64
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:var_i32]
+; CHECK-NEXT:    ldr x9, [x9, :got_lo12:var_i64]
+; CHECK-NEXT:    ldr w10, [x8]
+; CHECK-NEXT:    ldr x11, [x9]
+; CHECK-NEXT:    add w10, w10, #3567, lsl #12 // =14610432
+; CHECK-NEXT:    add x11, x11, #4095, lsl #12 // =16773120
+; CHECK-NEXT:    str w10, [x8]
+; CHECK-NEXT:    str x11, [x9]
+; CHECK-NEXT:    ret
 
-; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
   %val32 = load i32, i32* @var_i32
   %newval32 = add i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
-; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
   %val64 = load i64, i64* @var_i64
   %newval64 = add i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
@@ -73,13 +98,23 @@ define void @add_med() {
 ; Subtract 12-bit immediates
 define void @sub_small() {
 ; CHECK-LABEL: sub_small:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, :got:var_i32
+; CHECK-NEXT:    adrp x9, :got:var_i64
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:var_i32]
+; CHECK-NEXT:    ldr x9, [x9, :got_lo12:var_i64]
+; CHECK-NEXT:    ldr w10, [x8]
+; CHECK-NEXT:    ldr x11, [x9]
+; CHECK-NEXT:    sub w10, w10, #4095 // =4095
+; CHECK-NEXT:    sub x11, x11, #52 // =52
+; CHECK-NEXT:    str w10, [x8]
+; CHECK-NEXT:    str x11, [x9]
+; CHECK-NEXT:    ret
 
-; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
   %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 4095
   store i32 %newval32, i32* @var_i32
 
-; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52
   %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 52
   store i64 %newval64, i64* @var_i64
@@ -90,13 +125,23 @@ define void @sub_small() {
 ; Subtract 12-bit immediates, shifted left by 12 bits
 define void @sub_med() {
 ; CHECK-LABEL: sub_med:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, :got:var_i32
+; CHECK-NEXT:    adrp x9, :got:var_i64
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:var_i32]
+; CHECK-NEXT:    ldr x9, [x9, :got_lo12:var_i64]
+; CHECK-NEXT:    ldr w10, [x8]
+; CHECK-NEXT:    ldr x11, [x9]
+; CHECK-NEXT:    sub w10, w10, #3567, lsl #12 // =14610432
+; CHECK-NEXT:    sub x11, x11, #4095, lsl #12 // =16773120
+; CHECK-NEXT:    str w10, [x8]
+; CHECK-NEXT:    str x11, [x9]
+; CHECK-NEXT:    ret
 
-; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
   %val32 = load i32, i32* @var_i32
   %newval32 = sub i32 %val32, 14610432 ; =0xdef000
   store i32 %newval32, i32* @var_i32
 
-; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}}
   %val64 = load i64, i64* @var_i64
   %newval64 = sub i64 %val64, 16773120 ; =0xfff000
   store i64 %newval64, i64* @var_i64
@@ -106,41 +151,65 @@ define void @sub_med() {
 
 define void @testing() {
 ; CHECK-LABEL: testing:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, :got:var_i32
+; CHECK-NEXT:    ldr x8, [x8, :got_lo12:var_i32]
+; CHECK-NEXT:    ldr w9, [x8]
+; CHECK-NEXT:    cmp w9, #4095 // =4095
+; CHECK-NEXT:    b.ne .LBB5_6
+; CHECK-NEXT:  // %bb.1: // %test2
+; CHECK-NEXT:    adrp x10, :got:var2_i32
+; CHECK-NEXT:    ldr x10, [x10, :got_lo12:var2_i32]
+; CHECK-NEXT:    add w11, w9, #1 // =1
+; CHECK-NEXT:    str w11, [x8]
+; CHECK-NEXT:    ldr w10, [x10]
+; CHECK-NEXT:    cmp w10, #3567, lsl #12 // =14610432
+; CHECK-NEXT:    b.lo .LBB5_6
+; CHECK-NEXT:  // %bb.2: // %test3
+; CHECK-NEXT:    add w11, w9, #2 // =2
+; CHECK-NEXT:    cmp w9, #123 // =123
+; CHECK-NEXT:    str w11, [x8]
+; CHECK-NEXT:    b.lt .LBB5_6
+; CHECK-NEXT:  // %bb.3: // %test4
+; CHECK-NEXT:    add w11, w9, #3 // =3
+; CHECK-NEXT:    cmp w10, #321 // =321
+; CHECK-NEXT:    str w11, [x8]
+; CHECK-NEXT:    b.gt .LBB5_6
+; CHECK-NEXT:  // %bb.4: // %test5
+; CHECK-NEXT:    add w11, w9, #4 // =4
+; CHECK-NEXT:    cmn w10, #444 // =444
+; CHECK-NEXT:    str w11, [x8]
+; CHECK-NEXT:    b.gt .LBB5_6
+; CHECK-NEXT:  // %bb.5: // %test6
+; CHECK-NEXT:    add w9, w9, #5 // =5
+; CHECK-NEXT:    str w9, [x8]
+; CHECK-NEXT:  .LBB5_6: // %ret
+; CHECK-NEXT:    ret
   %val = load i32, i32* @var_i32
   %val2 = load i32, i32* @var2_i32
 
-; CHECK: cmp {{w[0-9]+}}, #4095
-; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]]
   %cmp_pos_small = icmp ne i32 %val, 4095
   br i1 %cmp_pos_small, label %ret, label %test2
 
 test2:
-; CHECK: cmp {{w[0-9]+}}, {{#3567, lsl #12|#14610432}}
-; CHECK: b.lo [[RET]]
   %newval2 = add i32 %val, 1
   store i32 %newval2, i32* @var_i32
   %cmp_pos_big = icmp ult i32 %val2, 14610432
   br i1 %cmp_pos_big, label %ret, label %test3
 
 test3:
-; CHECK: cmp {{w[0-9]+}}, #123
-; CHECK: b.lt [[RET]]
   %newval3 = add i32 %val, 2
   store i32 %newval3, i32* @var_i32
   %cmp_pos_slt = icmp slt i32 %val, 123
   br i1 %cmp_pos_slt, label %ret, label %test4
 
 test4:
-; CHECK: cmp {{w[0-9]+}}, #321
-; CHECK: b.gt [[RET]]
   %newval4 = add i32 %val, 3
   store i32 %newval4, i32* @var_i32
   %cmp_pos_sgt = icmp sgt i32 %val2, 321
   br i1 %cmp_pos_sgt, label %ret, label %test5
 
 test5:
-; CHECK: cmn {{w[0-9]+}}, #444
-; CHECK: b.gt [[RET]]
   %newval5 = add i32 %val, 4
   store i32 %newval5, i32* @var_i32
   %cmp_neg_uge = icmp sgt i32 %val2, -444

llvm/test/CodeGen/AArch64/branch-relax-alignment.ll

@@ -1,19 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=4 -align-all-nofallthru-blocks=4 < %s | FileCheck %s
 
 ; Long branch is assumed because the block has a higher alignment
 ; requirement than the function.
 
-; CHECK-LABEL: invert_bcc_block_align_higher_func:
-; CHECK: b.eq [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: b [[JUMP_BB2:LBB[0-9]+_[0-9]+]]
-
-; CHECK: [[JUMP_BB1]]:
-; CHECK: ret
-; CHECK: .p2align 4
-
-; CHECK: [[JUMP_BB2]]:
-; CHECK: ret
 define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 {
+; CHECK-LABEL: invert_bcc_block_align_higher_func:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    cmp w0, w1
+; CHECK-NEXT:    b.eq LBB0_1
+; CHECK-NEXT:    b LBB0_2
+; CHECK-NEXT:  LBB0_1: ; %bb1
+; CHECK-NEXT:    mov w8, #42
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    str w8, [x8]
+; CHECK-NEXT:    ret
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  LBB0_2: ; %bb2
+; CHECK-NEXT:    mov w8, #9
+; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    str w8, [x8]
+; CHECK-NEXT:    ret
   %1 = icmp eq i32 %x, %y
   br i1 %1, label %bb1, label %bb2
 

llvm/test/CodeGen/AArch64/branch-relax-bcc.ll

@@ -1,23 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
 
-; CHECK-LABEL: invert_bcc:
-; CHECK:      fcmp s0, s1
-; CHECK-NEXT: b.ne [[JUMP_BB1:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: b [[BB1:LBB[0-9]+_[0-9]+]]
-
-; CHECK-NEXT: [[JUMP_BB1]]:
-; CHECK-NEXT: b.vc [[BB2:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: b [[BB1]]
-
-; CHECK: [[BB2]]: ; %bb2
-; CHECK: mov w{{[0-9]+}}, #9
-; CHECK: ret
-
-; CHECK: [[BB1]]: ; %bb1
-; CHECK: mov w{{[0-9]+}}, #42
-; CHECK: ret
-
 define i32 @invert_bcc(float %x, float %y) #0 {
+; CHECK-LABEL: invert_bcc:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    fcmp s0, s1
+; CHECK-NEXT:    b.ne LBB0_3
+; CHECK-NEXT:    b LBB0_2
+; CHECK-NEXT:  LBB0_3:
+; CHECK-NEXT:    b.vc LBB0_1
+; CHECK-NEXT:    b LBB0_2
+; CHECK-NEXT:  LBB0_1: ; %bb2
+; CHECK-NEXT:    mov w8, #9
+; CHECK-NEXT:    mov w0, #1
+; CHECK-NEXT:    ; InlineAsm Start
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    ; InlineAsm End
+; CHECK-NEXT:    str w8, [x8]
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  LBB0_2: ; %bb1
+; CHECK-NEXT:    mov w8, #42
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    str w8, [x8]
+; CHECK-NEXT:    ret
   %1 = fcmp ueq float %x, %y
   br i1 %1, label %bb1, label %bb2
 
@@ -36,24 +42,26 @@ bb1:
 
 declare i32 @foo() #0
 
-; CHECK-LABEL: _block_split:
-; CHECK: cmp w0, #5
-; CHECK-NEXT: b.ne [[LOR_LHS_FALSE_BB:LBB[0-9]+_[0-9]+]]
-; CHECK-NEXT: b [[IF_THEN_BB:LBB[0-9]+_[0-9]+]]
-
-; CHECK: [[LOR_LHS_FALSE_BB]]:
-; CHECK: cmp w{{[0-9]+}}, #16
-; CHECK-NEXT: b.le [[IF_THEN_BB]]
-; CHECK-NEXT: b [[IF_END_BB:LBB[0-9]+_[0-9]+]]
-
-; CHECK: [[IF_THEN_BB]]:
-; CHECK: bl _foo
-; CHECK-NOT: b L
-
-; CHECK: [[IF_END_BB]]:
-; CHECK: mov{{.*}}, #7
-; CHECK: ret
 define i32 @block_split(i32 %a, i32 %b) #0 {
+; CHECK-LABEL: block_split:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    cmp w0, #5 ; =5
+; CHECK-NEXT:    b.ne LBB1_1
+; CHECK-NEXT:    b LBB1_2
+; CHECK-NEXT:  LBB1_1: ; %lor.lhs.false
+; CHECK-NEXT:    lsl w8, w1, #1
+; CHECK-NEXT:    cmp w1, #7 ; =7
+; CHECK-NEXT:    csinc w8, w8, w1, lt
+; CHECK-NEXT:    cmp w8, #16 ; =16
+; CHECK-NEXT:    b.le LBB1_2
+; CHECK-NEXT:    b LBB1_3
+; CHECK-NEXT:  LBB1_2: ; %if.then
+; CHECK-NEXT:    stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
+; CHECK-NEXT:    bl _foo
+; CHECK-NEXT:    ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
+; CHECK-NEXT:  LBB1_3: ; %if.end
+; CHECK-NEXT:    mov w0, #7
+; CHECK-NEXT:    ret
 entry:
   %cmp = icmp eq i32 %a, 5
   br i1 %cmp, label %if.then, label %lor.lhs.false