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[SelectionDAG] Add and use SDNode::getAsConstantVal() helper
This follows on from #76708, allowing `cast<ConstantSDNode>(N)->getZExtValue()` to be replaced with just `N2->getAsConstantVal();` Introduced via `git grep -l "cast<ConstantSDNode>\(.*\).*getZExtValue" | xargs sed -E -i 's/cast<ConstantSDNode>\((.*)\)->getZExtValue/\1->getAsConstantVal/'` and then using `git clang-format` on the result.
1 parent 5340347 commit e4ef2c1

40 files changed

+167
-189
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -923,6 +923,7 @@ END_TWO_BYTE_PACK()
923923

924924
/// Helper method returns the integer value of a ConstantSDNode operand.
925925
inline uint64_t getConstantOperandVal(unsigned Num) const;
926+
inline uint64_t getAsConstantVal() const;
926927

927928
/// Helper method returns the APInt of a ConstantSDNode operand.
928929
inline const APInt &getConstantOperandAPInt(unsigned Num) const;
@@ -1640,6 +1641,10 @@ uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
16401641
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
16411642
}
16421643

1644+
uint64_t SDNode::getAsConstantVal() const {
1645+
return cast<ConstantSDNode>(this)->getZExtValue();
1646+
}
1647+
16431648
const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
16441649
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
16451650
}

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14709,7 +14709,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
1470914709

1471014710
SDValue EltNo = N0->getOperand(1);
1471114711
if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
14712-
int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14712+
int Elt = EltNo->getAsConstantVal();
1471314713
int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
1471414714

1471514715
SDLoc DL(N);

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
551551
SDValue N0 = Node->getOperand(0);
552552
SDValue N1 = Node->getOperand(1);
553553
SDValue N2 = Node->getOperand(2);
554-
unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
554+
unsigned SubIdx = N2->getAsConstantVal();
555555

556556
// Figure out the register class to create for the destreg. It should be
557557
// the largest legal register class supporting SubIdx sub-registers.
@@ -650,7 +650,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
650650
// Skip physical registers as they don't have a vreg to get and we'll
651651
// insert copies for them in TwoAddressInstructionPass anyway.
652652
if (!R || !R->getReg().isPhysical()) {
653-
unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
653+
unsigned SubIdx = Op->getAsConstantVal();
654654
unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
655655
const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
656656
const TargetRegisterClass *SRC =

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2490,7 +2490,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
24902490
EVT VecVT = Vec->getValueType(0);
24912491
EVT EltVT = VecVT.getVectorElementType();
24922492

2493-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2493+
uint64_t IdxVal = Idx->getAsConstantVal();
24942494

24952495
switch (getTypeAction(VecVT)) {
24962496
default: break;

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5557,7 +5557,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
55575557
getTypeAction(InVT) == TargetLowering::TypeLegal) {
55585558
EVT NInVT = InVT.getHalfNumVectorElementsVT(*DAG.getContext());
55595559
unsigned NElts = NInVT.getVectorMinNumElements();
5560-
uint64_t IdxVal = cast<ConstantSDNode>(BaseIdx)->getZExtValue();
5560+
uint64_t IdxVal = BaseIdx->getAsConstantVal();
55615561

55625562
SDValue Step1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NInVT, InOp0,
55635563
DAG.getConstant(alignDown(IdxVal, NElts), dl,

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1442,7 +1442,7 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
14421442
std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
14431443

14441444
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
1445-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1445+
uint64_t IdxVal = Idx->getAsConstantVal();
14461446
Hi = DAG.getNode(
14471447
ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
14481448
DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl));
@@ -1466,7 +1466,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
14661466
// If we know the index is in the first half, and we know the subvector
14671467
// doesn't cross the boundary between the halves, we can avoid spilling the
14681468
// vector, and insert into the lower half of the split vector directly.
1469-
unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1469+
unsigned IdxVal = Idx->getAsConstantVal();
14701470
if (IdxVal + SubElems <= LoElems) {
14711471
Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
14721472
return;
@@ -3279,7 +3279,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_INSERT_SUBVECTOR(SDNode *N,
32793279
SDValue Lo, Hi;
32803280
GetSplitVector(SubVec, Lo, Hi);
32813281

3282-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3282+
uint64_t IdxVal = Idx->getAsConstantVal();
32833283
uint64_t LoElts = Lo.getValueType().getVectorMinNumElements();
32843284

32853285
SDValue FirstInsertion =
@@ -3301,7 +3301,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
33013301
GetSplitVector(N->getOperand(0), Lo, Hi);
33023302

33033303
uint64_t LoEltsMin = Lo.getValueType().getVectorMinNumElements();
3304-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3304+
uint64_t IdxVal = Idx->getAsConstantVal();
33053305

33063306
if (IdxVal < LoEltsMin) {
33073307
assert(IdxVal + SubVT.getVectorMinNumElements() <= LoEltsMin &&
@@ -5257,7 +5257,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
52575257
EVT InVT = InOp.getValueType();
52585258

52595259
// Check if we can just return the input vector after widening.
5260-
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5260+
uint64_t IdxVal = Idx->getAsConstantVal();
52615261
if (IdxVal == 0 && InVT == WidenVT)
52625262
return InOp;
52635263

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -7193,8 +7193,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
71937193
assert(isa<ConstantSDNode>(N3) &&
71947194
"Insert subvector index must be constant");
71957195
assert((VT.isScalableVector() != N2VT.isScalableVector() ||
7196-
(N2VT.getVectorMinNumElements() +
7197-
cast<ConstantSDNode>(N3)->getZExtValue()) <=
7196+
(N2VT.getVectorMinNumElements() + N3->getAsConstantVal()) <=
71987197
VT.getVectorMinNumElements()) &&
71997198
"Insert subvector overflow!");
72007199
assert(cast<ConstantSDNode>(N3)->getAPIntValue().getBitWidth() ==
@@ -9978,13 +9977,13 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
99789977
VTList.VTs[0].getVectorElementCount() ==
99799978
Ops[1].getValueType().getVectorElementCount()) &&
99809979
"Vector element count mismatch!");
9981-
assert(VTList.VTs[0].isFloatingPoint() &&
9982-
Ops[1].getValueType().isFloatingPoint() &&
9983-
VTList.VTs[0].bitsLT(Ops[1].getValueType()) &&
9984-
isa<ConstantSDNode>(Ops[2]) &&
9985-
(cast<ConstantSDNode>(Ops[2])->getZExtValue() == 0 ||
9986-
cast<ConstantSDNode>(Ops[2])->getZExtValue() == 1) &&
9987-
"Invalid STRICT_FP_ROUND!");
9980+
assert(
9981+
VTList.VTs[0].isFloatingPoint() &&
9982+
Ops[1].getValueType().isFloatingPoint() &&
9983+
VTList.VTs[0].bitsLT(Ops[1].getValueType()) &&
9984+
isa<ConstantSDNode>(Ops[2]) &&
9985+
(Ops[2]->getAsConstantVal() == 0 || Ops[2]->getAsConstantVal() == 1) &&
9986+
"Invalid STRICT_FP_ROUND!");
99889987
break;
99899988
#if 0
99909989
// FIXME: figure out how to safely handle things like

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5642,7 +5642,7 @@ static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL,
56425642
// expansion/promotion) if it was possible to expand a libcall of an
56435643
// illegal type during operation legalization. But it's not, so things
56445644
// get a bit hacky.
5645-
unsigned ScaleInt = cast<ConstantSDNode>(Scale)->getZExtValue();
5645+
unsigned ScaleInt = Scale->getAsConstantVal();
56465646
if ((ScaleInt > 0 || (Saturating && Signed)) &&
56475647
(TLI.isTypeLegal(VT) ||
56485648
(VT.isVector() && TLI.isTypeLegal(VT.getVectorElementType())))) {
@@ -7655,8 +7655,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
76557655
// suitable for the target. Convert the index as required.
76567656
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
76577657
if (Index.getValueType() != VectorIdxTy)
7658-
Index = DAG.getVectorIdxConstant(
7659-
cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7658+
Index = DAG.getVectorIdxConstant(Index->getAsConstantVal(), sdl);
76607659

76617660
EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
76627661
setValue(&I, DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, ResultVT, Vec, SubVec,
@@ -7672,8 +7671,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
76727671
// suitable for the target. Convert the index as required.
76737672
MVT VectorIdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
76747673
if (Index.getValueType() != VectorIdxTy)
7675-
Index = DAG.getVectorIdxConstant(
7676-
cast<ConstantSDNode>(Index)->getZExtValue(), sdl);
7674+
Index = DAG.getVectorIdxConstant(Index->getAsConstantVal(), sdl);
76777675

76787676
setValue(&I,
76797677
DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index));
@@ -8136,7 +8134,7 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
81368134
case ISD::VP_IS_FPCLASS: {
81378135
const DataLayout DLayout = DAG.getDataLayout();
81388136
EVT DestVT = TLI.getValueType(DLayout, VPIntrin.getType());
8139-
auto Constant = cast<ConstantSDNode>(OpValues[1])->getZExtValue();
8137+
auto Constant = OpValues[1]->getAsConstantVal();
81408138
SDValue Check = DAG.getTargetConstant(Constant, DL, MVT::i32);
81418139
SDValue V = DAG.getNode(ISD::VP_IS_FPCLASS, DL, DestVT,
81428140
{OpValues[0], Check, OpValues[2], OpValues[3]});
@@ -9173,8 +9171,7 @@ findMatchingInlineAsmOperand(unsigned OperandNo,
91739171
unsigned CurOp = InlineAsm::Op_FirstOperand;
91749172
for (; OperandNo; --OperandNo) {
91759173
// Advance to the next operand.
9176-
unsigned OpFlag =
9177-
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
9174+
unsigned OpFlag = AsmNodeOperands[CurOp]->getAsConstantVal();
91789175
const InlineAsm::Flag F(OpFlag);
91799176
assert(
91809177
(F.isRegDefKind() || F.isRegDefEarlyClobberKind() || F.isMemKind()) &&
@@ -9480,8 +9477,7 @@ void SelectionDAGBuilder::visitInlineAsm(const CallBase &Call,
94809477
// just use its register.
94819478
auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
94829479
AsmNodeOperands);
9483-
InlineAsm::Flag Flag(
9484-
cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue());
9480+
InlineAsm::Flag Flag(AsmNodeOperands[CurOp]->getAsConstantVal());
94859481
if (Flag.isRegDefKind() || Flag.isRegDefEarlyClobberKind()) {
94869482
if (OpInfo.isIndirect) {
94879483
// This happens on gcc/testsuite/gcc.dg/pr8788-1.c
@@ -9985,14 +9981,14 @@ void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
99859981
// constant nodes.
99869982
SDValue ID = getValue(CI.getArgOperand(0));
99879983
assert(ID.getValueType() == MVT::i64);
9988-
SDValue IDConst = DAG.getTargetConstant(
9989-
cast<ConstantSDNode>(ID)->getZExtValue(), DL, ID.getValueType());
9984+
SDValue IDConst =
9985+
DAG.getTargetConstant(ID->getAsConstantVal(), DL, ID.getValueType());
99909986
Ops.push_back(IDConst);
99919987

99929988
SDValue Shad = getValue(CI.getArgOperand(1));
99939989
assert(Shad.getValueType() == MVT::i32);
9994-
SDValue ShadConst = DAG.getTargetConstant(
9995-
cast<ConstantSDNode>(Shad)->getZExtValue(), DL, Shad.getValueType());
9990+
SDValue ShadConst =
9991+
DAG.getTargetConstant(Shad->getAsConstantVal(), DL, Shad.getValueType());
99969992
Ops.push_back(ShadConst);
99979993

99989994
// Add the live variables.
@@ -10041,7 +10037,7 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
1004110037

1004210038
// Get the real number of arguments participating in the call <numArgs>
1004310039
SDValue NArgVal = getValue(CB.getArgOperand(PatchPointOpers::NArgPos));
10044-
unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
10040+
unsigned NumArgs = NArgVal->getAsConstantVal();
1004510041

1004610042
// Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
1004710043
// Intrinsics include all meta-operands up to but not including CC.
@@ -10088,12 +10084,10 @@ void SelectionDAGBuilder::visitPatchpoint(const CallBase &CB,
1008810084

1008910085
// Add the <id> and <numBytes> constants.
1009010086
SDValue IDVal = getValue(CB.getArgOperand(PatchPointOpers::IDPos));
10091-
Ops.push_back(DAG.getTargetConstant(
10092-
cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
10087+
Ops.push_back(DAG.getTargetConstant(IDVal->getAsConstantVal(), dl, MVT::i64));
1009310088
SDValue NBytesVal = getValue(CB.getArgOperand(PatchPointOpers::NBytesPos));
10094-
Ops.push_back(DAG.getTargetConstant(
10095-
cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
10096-
MVT::i32));
10089+
Ops.push_back(
10090+
DAG.getTargetConstant(NBytesVal->getAsConstantVal(), dl, MVT::i32));
1009710091

1009810092
// Add the callee.
1009910093
Ops.push_back(Callee);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
149149
case ISD::INTRINSIC_VOID:
150150
case ISD::INTRINSIC_W_CHAIN: {
151151
unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
152-
unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
152+
unsigned IID = getOperand(OpNo)->getAsConstantVal();
153153
if (IID < Intrinsic::num_intrinsics)
154154
return Intrinsic::getBaseName((Intrinsic::ID)IID).str();
155155
if (!G)

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2121,7 +2121,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
21212121
--e; // Don't process a glue operand if it is here.
21222122

21232123
while (i != e) {
2124-
InlineAsm::Flag Flags(cast<ConstantSDNode>(InOps[i])->getZExtValue());
2124+
InlineAsm::Flag Flags(InOps[i]->getAsConstantVal());
21252125
if (!Flags.isMemKind() && !Flags.isFuncKind()) {
21262126
// Just skip over this operand, copying the operands verbatim.
21272127
Ops.insert(Ops.end(), InOps.begin() + i,
@@ -2135,12 +2135,10 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
21352135
if (Flags.isUseOperandTiedToDef(TiedToOperand)) {
21362136
// We need the constraint ID from the operand this is tied to.
21372137
unsigned CurOp = InlineAsm::Op_FirstOperand;
2138-
Flags =
2139-
InlineAsm::Flag(cast<ConstantSDNode>(InOps[CurOp])->getZExtValue());
2138+
Flags = InlineAsm::Flag(InOps[CurOp]->getAsConstantVal());
21402139
for (; TiedToOperand; --TiedToOperand) {
21412140
CurOp += Flags.getNumOperandRegisters() + 1;
2142-
Flags = InlineAsm::Flag(
2143-
cast<ConstantSDNode>(InOps[CurOp])->getZExtValue());
2141+
Flags = InlineAsm::Flag(InOps[CurOp]->getAsConstantVal());
21442142
}
21452143
}
21462144

@@ -2380,9 +2378,8 @@ void SelectionDAGISel::pushStackMapLiveVariable(SmallVectorImpl<SDValue> &Ops,
23802378
if (OpNode->getOpcode() == ISD::Constant) {
23812379
Ops.push_back(
23822380
CurDAG->getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
2383-
Ops.push_back(
2384-
CurDAG->getTargetConstant(cast<ConstantSDNode>(OpNode)->getZExtValue(),
2385-
DL, OpVal.getValueType()));
2381+
Ops.push_back(CurDAG->getTargetConstant(OpNode->getAsConstantVal(), DL,
2382+
OpVal.getValueType()));
23862383
} else {
23872384
Ops.push_back(OpVal);
23882385
}
@@ -2452,7 +2449,7 @@ void SelectionDAGISel::Select_PATCHPOINT(SDNode *N) {
24522449
Ops.push_back(*It++);
24532450

24542451
// Push the args for the call.
2455-
for (uint64_t I = cast<ConstantSDNode>(NumArgs)->getZExtValue(); I != 0; I--)
2452+
for (uint64_t I = NumArgs->getAsConstantVal(); I != 0; I--)
24562453
Ops.push_back(*It++);
24572454

24582455
// Now push the live variables.

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -580,7 +580,7 @@ bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
580580
if (!isa<ConstantSDNode>(N.getNode()))
581581
return false;
582582

583-
uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
583+
uint64_t Immed = N.getNode()->getAsConstantVal();
584584
unsigned ShiftAmt;
585585

586586
if (Immed >> 12 == 0) {
@@ -611,7 +611,7 @@ bool AArch64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
611611
return false;
612612

613613
// The immediate operand must be a 24-bit zero-extended immediate.
614-
uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
614+
uint64_t Immed = N.getNode()->getAsConstantVal();
615615

616616
// This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
617617
// have the opposite effect on the C flag, so this pattern mustn't match under
@@ -1326,7 +1326,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeXRO(SDValue N, unsigned Size,
13261326
// MOV X0, WideImmediate
13271327
// LDR X2, [BaseReg, X0]
13281328
if (isa<ConstantSDNode>(RHS)) {
1329-
int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
1329+
int64_t ImmOff = (int64_t)RHS->getAsConstantVal();
13301330
// Skip the immediate can be selected by load/store addressing mode.
13311331
// Also skip the immediate can be encoded by a single ADD (SUB is also
13321332
// checked by using -ImmOff).

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3589,7 +3589,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
35893589
// can be turned into:
35903590
// cmp w12, w11, lsl #1
35913591
if (!isa<ConstantSDNode>(RHS) ||
3592-
!isLegalArithImmed(cast<ConstantSDNode>(RHS)->getZExtValue())) {
3592+
!isLegalArithImmed(RHS->getAsConstantVal())) {
35933593
SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;
35943594

35953595
if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
@@ -3623,7 +3623,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
36233623
cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
36243624
cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
36253625
LHS.getNode()->hasNUsesOfValue(1, 0)) {
3626-
int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
3626+
int16_t ValueofRHS = RHS->getAsConstantVal();
36273627
if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
36283628
SDValue SExt =
36293629
DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
@@ -5619,7 +5619,7 @@ SDValue AArch64TargetLowering::LowerMGATHER(SDValue Op,
56195619

56205620
// SVE supports an index scaled by sizeof(MemVT.elt) only, everything else
56215621
// must be calculated before hand.
5622-
uint64_t ScaleVal = cast<ConstantSDNode>(Scale)->getZExtValue();
5622+
uint64_t ScaleVal = Scale->getAsConstantVal();
56235623
if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) {
56245624
assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types");
56255625
EVT IndexVT = Index.getValueType();
@@ -5707,7 +5707,7 @@ SDValue AArch64TargetLowering::LowerMSCATTER(SDValue Op,
57075707

57085708
// SVE supports an index scaled by sizeof(MemVT.elt) only, everything else
57095709
// must be calculated before hand.
5710-
uint64_t ScaleVal = cast<ConstantSDNode>(Scale)->getZExtValue();
5710+
uint64_t ScaleVal = Scale->getAsConstantVal();
57115711
if (IsScaled && ScaleVal != MemVT.getScalarStoreSize()) {
57125712
assert(isPowerOf2_64(ScaleVal) && "Expecting power-of-two types");
57135713
EVT IndexVT = Index.getValueType();
@@ -22011,7 +22011,7 @@ static SDValue performBRCONDCombine(SDNode *N,
2201122011
SDValue Cmp = N->getOperand(3);
2201222012

2201322013
assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
22014-
unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
22014+
unsigned CC = CCVal->getAsConstantVal();
2201522015
if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
2201622016
return SDValue();
2201722017

‎llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -172,7 +172,7 @@ static SDValue EmitUnrolledSetTag(SelectionDAG &DAG, const SDLoc &dl,
172172
SDValue AArch64SelectionDAGInfo::EmitTargetCodeForSetTag(
173173
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr,
174174
SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const {
175-
uint64_t ObjSize = cast<ConstantSDNode>(Size)->getZExtValue();
175+
uint64_t ObjSize = Size->getAsConstantVal();
176176
assert(ObjSize % 16 == 0);
177177

178178
MachineFunction &MF = DAG.getMachineFunction();

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -382,7 +382,7 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
382382
Subtarget->getRegisterInfo()->getRegClass(RCID);
383383

384384
SDValue SubRegOp = N->getOperand(OpNo + 1);
385-
unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
385+
unsigned SubRegIdx = SubRegOp->getAsConstantVal();
386386
return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
387387
SubRegIdx);
388388
}

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