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wangpc-ppwangpc-pp
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Use VP nodes and rebase on #115162
Created using spr 1.3.6-beta.1
2 parents 5dfa889 + 7cf605e commit e57dde9

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7 files changed

+39
-81
lines changed

7 files changed

+39
-81
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3708,6 +3708,15 @@ static bool isImplicitDef(SDValue V) {
37083708
return V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
37093709
}
37103710

3711+
static bool hasGPROut(unsigned Opc) {
3712+
switch (RISCV::getRVVMCOpcode(Opc)) {
3713+
case RISCV::VCPOP_M:
3714+
case RISCV::VFIRST_M:
3715+
return true;
3716+
}
3717+
return false;
3718+
}
3719+
37113720
// Optimize masked RVV pseudo instructions with a known all-ones mask to their
37123721
// corresponding "unmasked" pseudo versions. The mask we're interested in will
37133722
// take the form of a V0 physical register operand, with a glued
@@ -3737,8 +3746,9 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
37373746
#endif
37383747

37393748
SmallVector<SDValue, 8> Ops;
3740-
// Skip the passthru operand at index 0 if !UseTUPseudo.
3741-
for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
3749+
// Skip the passthru operand at index 0 if !UseTUPseudo and no GPR out.
3750+
bool ShouldSkip = !UseTUPseudo && !hasGPROut(Opc);
3751+
for (unsigned I = ShouldSkip, E = N->getNumOperands(); I != E; I++) {
37423752
// Skip the mask, and the Glue.
37433753
SDValue Op = N->getOperand(I);
37443754
if (I == MaskOpIdx || Op.getValueType() == MVT::Glue)

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14564,8 +14564,15 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC,
1456414564

1456514565
SDValue VecX = DAG.getBitcast(VecVT, X);
1456614566
SDValue VecY = DAG.getBitcast(VecVT, Y);
14567-
SDValue Cmp = DAG.getSetCC(DL, CmpVT, VecX, VecY, ISD::SETNE);
14568-
return DAG.getSetCC(DL, VT, DAG.getNode(ISD::VECREDUCE_OR, DL, XLenVT, Cmp),
14567+
SDValue Mask = DAG.getAllOnesConstant(DL, CmpVT);
14568+
SDValue VL = DAG.getConstant(VecSize, DL, XLenVT);
14569+
14570+
SDValue Cmp = DAG.getNode(ISD::VP_SETCC, DL, CmpVT, VecX, VecY,
14571+
DAG.getCondCode(ISD::SETNE), Mask, VL);
14572+
return DAG.getSetCC(DL, VT,
14573+
DAG.getNode(ISD::VP_REDUCE_OR, DL, XLenVT,
14574+
DAG.getConstant(0, DL, XLenVT), Cmp, Mask,
14575+
VL),
1456914576
DAG.getConstant(0, DL, XLenVT), CC);
1457014577
}
1457114578

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1150,6 +1150,7 @@ class VPseudoUnaryNoMaskGPROut :
11501150
class VPseudoUnaryMaskGPROut :
11511151
Pseudo<(outs GPR:$rd),
11521152
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>,
1153+
RISCVMaskedPseudo<MaskIdx=1>,
11531154
RISCVVPseudo {
11541155
let mayLoad = 0;
11551156
let mayStore = 0;

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2527,7 +2527,7 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
25272527
Options.LoadSizes = {8, 4, 2, 1};
25282528
else
25292529
Options.LoadSizes = {4, 2, 1};
2530-
if (IsZeroCmp && ST->hasVInstructions()) {
2530+
if (IsZeroCmp && ST->hasVInstructions() && ST->enableUnalignedVectorMem()) {
25312531
unsigned VLenB = ST->getRealMinVLen() / 8;
25322532
// The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
25332533
// and `XLen * 2`.

‎llvm/test/CodeGen/RISCV/memcmp-optsize.ll

Lines changed: 7 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1072,11 +1072,8 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind optsize {
10721072
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 15, e8, m1, ta, ma
10731073
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
10741074
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v9, (a1)
1075-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1076-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
10771075
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v9
1078-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 15, e8, m1, ta, ma
1079-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8, v0.t
1076+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
10801077
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
10811078
; CHECK-UNALIGNED-RV32-V-NEXT: ret
10821079
;
@@ -1473,12 +1470,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize {
14731470
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
14741471
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
14751472
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
1476-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 32
1477-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1478-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
14791473
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
1480-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
1481-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12, v0.t
1474+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
14821475
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
14831476
; CHECK-UNALIGNED-RV32-V-NEXT: ret
14841477
;
@@ -1487,12 +1480,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind optsize {
14871480
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
14881481
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
14891482
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
1490-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 32
1491-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1492-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
14931483
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
1494-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
1495-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12, v0.t
1484+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
14961485
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
14971486
; CHECK-UNALIGNED-RV64-V-NEXT: ret
14981487
entry:
@@ -1844,12 +1833,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind optsize {
18441833
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
18451834
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
18461835
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
1847-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 64
1848-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1849-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
18501836
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
1851-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
1852-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16, v0.t
1837+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
18531838
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
18541839
; CHECK-UNALIGNED-RV32-V-NEXT: ret
18551840
;
@@ -1859,12 +1844,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind optsize {
18591844
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
18601845
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
18611846
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
1862-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 64
1863-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1864-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
18651847
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
1866-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
1867-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16, v0.t
1848+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
18681849
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
18691850
; CHECK-UNALIGNED-RV64-V-NEXT: ret
18701851
entry:
@@ -2186,12 +2167,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind optsize {
21862167
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
21872168
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
21882169
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2189-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 128
2190-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m8, ta, ma
2191-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
21922170
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2193-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
2194-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24, v0.t
2171+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
21952172
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
21962173
; CHECK-UNALIGNED-RV32-V-NEXT: ret
21972174
;
@@ -2201,12 +2178,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind optsize {
22012178
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
22022179
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
22032180
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2204-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 128
2205-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m8, ta, ma
2206-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
22072181
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2208-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
2209-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24, v0.t
2182+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
22102183
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
22112184
; CHECK-UNALIGNED-RV64-V-NEXT: ret
22122185
entry:

‎llvm/test/CodeGen/RISCV/memcmp.ll

Lines changed: 7 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1072,11 +1072,8 @@ define i32 @bcmp_size_15(ptr %s1, ptr %s2) nounwind {
10721072
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 15, e8, m1, ta, ma
10731073
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
10741074
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v9, (a1)
1075-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 16, e8, m1, ta, ma
1076-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
10771075
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v8, v8, v9
1078-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 15, e8, m1, ta, ma
1079-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8, v0.t
1076+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v8
10801077
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
10811078
; CHECK-UNALIGNED-RV32-V-NEXT: ret
10821079
;
@@ -1551,12 +1548,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind {
15511548
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
15521549
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
15531550
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v10, (a1)
1554-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 32
1555-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1556-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
15571551
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v12, v8, v10
1558-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
1559-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12, v0.t
1552+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v12
15601553
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
15611554
; CHECK-UNALIGNED-RV32-V-NEXT: ret
15621555
;
@@ -1565,12 +1558,8 @@ define i32 @bcmp_size_31(ptr %s1, ptr %s2) nounwind {
15651558
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
15661559
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
15671560
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v10, (a1)
1568-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 32
1569-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1570-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
15711561
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v12, v8, v10
1572-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetivli zero, 31, e8, m2, ta, ma
1573-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12, v0.t
1562+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v12
15741563
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
15751564
; CHECK-UNALIGNED-RV64-V-NEXT: ret
15761565
entry:
@@ -2078,12 +2067,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind {
20782067
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
20792068
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
20802069
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v12, (a1)
2081-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 64
2082-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
2083-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
20842070
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v16, v8, v12
2085-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
2086-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16, v0.t
2071+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v16
20872072
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
20882073
; CHECK-UNALIGNED-RV32-V-NEXT: ret
20892074
;
@@ -2093,12 +2078,8 @@ define i32 @bcmp_size_63(ptr %s1, ptr %s2) nounwind {
20932078
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
20942079
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
20952080
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v12, (a1)
2096-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 64
2097-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m4, ta, ma
2098-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
20992081
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v16, v8, v12
2100-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m4, ta, ma
2101-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16, v0.t
2082+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v16
21022083
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
21032084
; CHECK-UNALIGNED-RV64-V-NEXT: ret
21042085
entry:
@@ -2498,12 +2479,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind {
24982479
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
24992480
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v8, (a0)
25002481
; CHECK-UNALIGNED-RV32-V-NEXT: vle8.v v16, (a1)
2501-
; CHECK-UNALIGNED-RV32-V-NEXT: li a0, 128
2502-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a0, e8, m8, ta, ma
2503-
; CHECK-UNALIGNED-RV32-V-NEXT: vmset.m v0
25042482
; CHECK-UNALIGNED-RV32-V-NEXT: vmsne.vv v24, v8, v16
2505-
; CHECK-UNALIGNED-RV32-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
2506-
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24, v0.t
2483+
; CHECK-UNALIGNED-RV32-V-NEXT: vcpop.m a0, v24
25072484
; CHECK-UNALIGNED-RV32-V-NEXT: snez a0, a0
25082485
; CHECK-UNALIGNED-RV32-V-NEXT: ret
25092486
;
@@ -2513,12 +2490,8 @@ define i32 @bcmp_size_127(ptr %s1, ptr %s2) nounwind {
25132490
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
25142491
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v8, (a0)
25152492
; CHECK-UNALIGNED-RV64-V-NEXT: vle8.v v16, (a1)
2516-
; CHECK-UNALIGNED-RV64-V-NEXT: li a0, 128
2517-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a0, e8, m8, ta, ma
2518-
; CHECK-UNALIGNED-RV64-V-NEXT: vmset.m v0
25192493
; CHECK-UNALIGNED-RV64-V-NEXT: vmsne.vv v24, v8, v16
2520-
; CHECK-UNALIGNED-RV64-V-NEXT: vsetvli zero, a2, e8, m8, ta, ma
2521-
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24, v0.t
2494+
; CHECK-UNALIGNED-RV64-V-NEXT: vcpop.m a0, v24
25222495
; CHECK-UNALIGNED-RV64-V-NEXT: snez a0, a0
25232496
; CHECK-UNALIGNED-RV64-V-NEXT: ret
25242497
entry:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1797,11 +1797,8 @@ define float @vreduce_fminimum_v7f32(ptr %x) {
17971797
; CHECK: # %bb.0:
17981798
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
17991799
; CHECK-NEXT: vle32.v v8, (a0)
1800-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
1801-
; CHECK-NEXT: vmset.m v0
1802-
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
18031800
; CHECK-NEXT: vmfne.vv v10, v8, v8
1804-
; CHECK-NEXT: vcpop.m a0, v10, v0.t
1801+
; CHECK-NEXT: vcpop.m a0, v10
18051802
; CHECK-NEXT: beqz a0, .LBB111_2
18061803
; CHECK-NEXT: # %bb.1:
18071804
; CHECK-NEXT: lui a0, 523264
@@ -2558,11 +2555,8 @@ define float @vreduce_fmaximum_v7f32(ptr %x) {
25582555
; CHECK: # %bb.0:
25592556
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
25602557
; CHECK-NEXT: vle32.v v8, (a0)
2561-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
2562-
; CHECK-NEXT: vmset.m v0
2563-
; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
25642558
; CHECK-NEXT: vmfne.vv v10, v8, v8
2565-
; CHECK-NEXT: vcpop.m a0, v10, v0.t
2559+
; CHECK-NEXT: vcpop.m a0, v10
25662560
; CHECK-NEXT: beqz a0, .LBB139_2
25672561
; CHECK-NEXT: # %bb.1:
25682562
; CHECK-NEXT: lui a0, 523264

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