Skip to content

Commit e59a0cd

Browse files
MDevereauMDevereau
authored
[AArch64][SME2] Add SME2 builtins for zero { zt0 } (#72274)
See ARM-software/acle#217 Patch by: Kerry McLaughlin [email protected]
1 parent f42b761 commit e59a0cd

File tree

8 files changed

+74
-14
lines changed

8 files changed

+74
-14
lines changed

‎clang/include/clang/Basic/arm_sme.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -321,4 +321,9 @@ let TargetGuard = "sme2" in {
321321
let TargetGuard = "sme2" in {
322322
def SVLDR_ZT : Inst<"svldr_zt", "viQ", "", MergeNone, "aarch64_sme_ldr_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
323323
def SVSTR_ZT : Inst<"svstr_zt", "vi%", "", MergeNone, "aarch64_sme_str_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA], [ImmCheck<0, ImmCheck0_0>]>;
324+
325+
//
326+
// Zero ZT0
327+
//
328+
def SVZERO_ZT : Inst<"svzero_zt", "vi", "", MergeNone, "aarch64_sme_zero_zt", [IsOverloadNone, IsStreamingCompatible, IsSharedZA], [ImmCheck<0, ImmCheck0_0>]>;
324329
}

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_zero_zt.c

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2+
3+
// REQUIRES: aarch64-registered-target
4+
5+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
6+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
7+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
8+
9+
#include <arm_sme_draft_spec_subject_to_change.h>
10+
11+
// CHECK-LABEL: @test_svzero_zt(
12+
// CHECK-NEXT: entry:
13+
// CHECK-NEXT: tail call void @llvm.aarch64.sme.zero.zt(i32 0)
14+
// CHECK-NEXT: ret void
15+
//
16+
// CPP-CHECK-LABEL: @_Z14test_svzero_ztv(
17+
// CPP-CHECK-NEXT: entry:
18+
// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.zero.zt(i32 0)
19+
// CPP-CHECK-NEXT: ret void
20+
//
21+
void test_svzero_zt(void) __arm_streaming_compatible __arm_shared_za {
22+
svzero_zt(0);
23+
}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3544,6 +3544,10 @@ let TargetPrefix = "aarch64" in {
35443544
def int_aarch64_sme_ldr_zt : SME_LDR_STR_ZT_Intrinsic;
35453545
def int_aarch64_sme_str_zt : SME_LDR_STR_ZT_Intrinsic;
35463546

3547+
//
3548+
// Zero ZT0
3549+
//
3550+
def int_aarch64_sme_zero_zt : DefaultAttrsIntrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>, IntrWriteMem]>;
35473551
}
35483552

35493553
// SVE2.1 - ZIPQ1, ZIPQ2, UZPQ1, UZPQ2

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2753,17 +2753,19 @@ AArch64TargetLowering::EmitFill(MachineInstr &MI, MachineBasicBlock *BB) const {
27532753
return BB;
27542754
}
27552755

2756-
MachineBasicBlock *AArch64TargetLowering::EmitZTSpillFill(MachineInstr &MI,
2757-
MachineBasicBlock *BB,
2758-
bool IsSpill) const {
2756+
MachineBasicBlock *AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
2757+
MachineBasicBlock *BB,
2758+
unsigned Opcode,
2759+
bool Op0IsDef) const {
27592760
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
27602761
MachineInstrBuilder MIB;
2761-
unsigned Opc = IsSpill ? AArch64::STR_TX : AArch64::LDR_TX;
2762-
auto Rs = IsSpill ? RegState::Kill : RegState::Define;
2763-
MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opc));
2764-
MIB.addReg(MI.getOperand(0).getReg(), Rs);
2765-
MIB.add(MI.getOperand(1)); // Base
2766-
MI.eraseFromParent(); // The pseudo is gone now.
2762+
2763+
MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Opcode))
2764+
.addReg(MI.getOperand(0).getReg(), Op0IsDef ? RegState::Define : 0);
2765+
for (unsigned I = 1; I < MI.getNumOperands(); ++I)
2766+
MIB.add(MI.getOperand(I));
2767+
2768+
MI.eraseFromParent(); // The pseudo is gone now.
27672769
return BB;
27682770
}
27692771

@@ -2884,11 +2886,13 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
28842886
case AArch64::LDR_ZA_PSEUDO:
28852887
return EmitFill(MI, BB);
28862888
case AArch64::LDR_TX_PSEUDO:
2887-
return EmitZTSpillFill(MI, BB, /*IsSpill=*/false);
2889+
return EmitZTInstr(MI, BB, AArch64::LDR_TX, /*Op0IsDef=*/true);
28882890
case AArch64::STR_TX_PSEUDO:
2889-
return EmitZTSpillFill(MI, BB, /*IsSpill=*/true);
2891+
return EmitZTInstr(MI, BB, AArch64::STR_TX, /*Op0IsDef=*/false);
28902892
case AArch64::ZERO_M_PSEUDO:
28912893
return EmitZero(MI, BB);
2894+
case AArch64::ZERO_T_PSEUDO:
2895+
return EmitZTInstr(MI, BB, AArch64::ZERO_T, /*Op0IsDef=*/true);
28922896
}
28932897
}
28942898

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -623,8 +623,8 @@ class AArch64TargetLowering : public TargetLowering {
623623
MachineBasicBlock *EmitZAInstr(unsigned Opc, unsigned BaseReg,
624624
MachineInstr &MI, MachineBasicBlock *BB,
625625
bool HasTile) const;
626-
MachineBasicBlock *EmitZTSpillFill(MachineInstr &MI, MachineBasicBlock *BB,
627-
bool IsSpill) const;
626+
MachineBasicBlock *EmitZTInstr(MachineInstr &MI, MachineBasicBlock *BB,
627+
unsigned Opcode, bool Op0IsDef) const;
628628
MachineBasicBlock *EmitZero(MachineInstr &MI, MachineBasicBlock *BB) const;
629629

630630
MachineBasicBlock *

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -539,7 +539,7 @@ defm SMOPS_MPPZZ_HtoS : sme2_int_mopx_tile<"smops", 0b001, int_aarch64_sme_smops
539539
defm UMOPA_MPPZZ_HtoS : sme2_int_mopx_tile<"umopa", 0b100, int_aarch64_sme_umopa_za32>;
540540
defm UMOPS_MPPZZ_HtoS : sme2_int_mopx_tile<"umops", 0b101, int_aarch64_sme_umops_za32>;
541541

542-
def ZERO_T : sme2_zero_zt<"zero", 0b0001>;
542+
defm ZERO_T : sme2_zero_zt<"zero", 0b0001>;
543543

544544
defm LDR_TX : sme2_spill_fill_vector<"ldr", 0b01111100, int_aarch64_sme_ldr_zt>;
545545
defm STR_TX : sme2_spill_fill_vector<"str", 0b11111100, int_aarch64_sme_str_zt>;

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3119,6 +3119,17 @@ class sme2_zero_zt<string mnemonic, bits<4> opc>
31193119
let Inst{3-0} = opc;
31203120
}
31213121

3122+
multiclass sme2_zero_zt<string mnemonic, bits<4> opc> {
3123+
def NAME : sme2_zero_zt<mnemonic, opc>;
3124+
def NAME # _PSEUDO
3125+
: Pseudo<(outs), (ins ZTR:$ZT), []>, Sched<[]> {
3126+
// Translated to actual instruction in AArch64ISelLowering.cpp
3127+
let usesCustomInserter = 1;
3128+
}
3129+
def : Pat<(int_aarch64_sme_zero_zt (imm_to_zt untyped:$zt)),
3130+
(!cast<Instruction>(NAME # _PSEUDO) $zt)>;
3131+
}
3132+
31223133
//===----------------------------------------------------------------------===//
31233134
// SME2 lookup table load/store
31243135
class sme2_spill_fill_vector<string mnemonic, bits<8> opc>

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-zero-zt.ll

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 < %s | FileCheck %s
3+
4+
define void @zero_zt0() {
5+
; CHECK-LABEL: zero_zt0:
6+
; CHECK: // %bb.0:
7+
; CHECK-NEXT: zero { zt0 }
8+
; CHECK-NEXT: ret
9+
call void @llvm.aarch64.sme.zero.zt(i32 0)
10+
ret void
11+
}
12+
13+
declare void @llvm.aarch64.sme.zero.zt(i32)

0 commit comments

Comments
 (0)