Clang: don't unnecessarily convert inline-asm operands to x86mmx in IR. (#98273)

The SelectionDAG asm-lowering code can already handle conversion of
other vector types to MMX if needed.

Author: jyknight

clang/lib/CodeGen/Targets/X86.cpp

@@ -24,22 +24,9 @@ bool IsX86_MMXType(llvm::Type *IRType) {
     IRType->getScalarSizeInBits() != 64;
 }
 
-static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
+static llvm::Type *X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
                                           StringRef Constraint,
-                                          llvm::Type* Ty) {
-  bool IsMMXCons = llvm::StringSwitch<bool>(Constraint)
-                     .Cases("y", "&y", "^Ym", true)
-                     .Default(false);
-  if (IsMMXCons && Ty->isVectorTy()) {
-    if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() !=
-        64) {
-      // Invalid MMX constraint
-      return nullptr;
-    }
-
-    return llvm::Type::getX86_MMXTy(CGF.getLLVMContext());
-  }
-
+                                          llvm::Type *Ty) {
   if (Constraint == "k") {
     llvm::Type *Int1Ty = llvm::Type::getInt1Ty(CGF.getLLVMContext());
     return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());

clang/test/CodeGen/X86/mmx-inline-asm.c

@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -emit-llvm -triple i386 -target-feature +mmx %s -o - | FileCheck %s
 #include <mmintrin.h>
 
-// CHECK: { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx }
+// CHECK: { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> }
 
 void foo(long long fill) {
   __m64 vfill = _mm_cvtsi64_m64(fill);

clang/test/CodeGen/asm-inout.c

@@ -38,11 +38,11 @@ int test4(volatile int *addr) {
   return (int)oldval;
 }
 
-// This should have both inputs be of type x86_mmx.
+// This should have both inputs be of type <1 x i64>.
 // CHECK: @test5
 typedef long long __m64 __attribute__((__vector_size__(8)));
 __m64 test5(__m64 __A, __m64 __B) {
-  // CHECK: call x86_mmx asm "pmulhuw $1, $0\0A\09", "=y,y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %{{.*}}, x86_mmx %{{.*}})
+  // CHECK: call <1 x i64> asm "pmulhuw $1, $0\0A\09", "=y,y,0,~{dirflag},~{fpsr},~{flags}"(<1 x i64> %{{.*}}, <1 x i64> %{{.*}})
   asm ("pmulhuw %1, %0\n\t" : "+y" (__A) : "y" (__B));
   return __A;
 }
@@ -51,7 +51,7 @@ __m64 test5(__m64 __A, __m64 __B) {
 int test6(void) {
   typedef unsigned char __attribute__((vector_size(8))) _m64u8;
   _m64u8 __attribute__((aligned(16))) Mu8_0, __attribute__((aligned(16))) Mu8_1;
-  // CHECK: call x86_mmx asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(x86_mmx %1)
+  // CHECK: call <8 x i8> asm "nop", "=y,0,~{dirflag},~{fpsr},~{flags}"(<8 x i8> %0)
   asm ("nop" : "=y"(Mu8_1 ) : "0"(Mu8_0 ));
   return 0;
 }

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -58378,7 +58378,7 @@ X86TargetLowering::getSingleConstraintMatchWeight(
       Wt = CW_SpecificReg;
     break;
   case 'y':
-    if (Ty->isX86_MMXTy() && Subtarget.hasMMX())
+    if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX())
       Wt = CW_SpecificReg;
     break;
   case 'Y':
@@ -58401,8 +58401,8 @@ X86TargetLowering::getSingleConstraintMatchWeight(
       return CW_Invalid;
     // Any MMX reg
     case 'm':
-      if (Ty->isX86_MMXTy() && Subtarget.hasMMX())
-        return Wt;
+      if (Ty->getPrimitiveSizeInBits() == 64 && Subtarget.hasMMX())
+        return CW_SpecificReg;
       return CW_Invalid;
     // Any SSE reg when ISA >= SSE2, same as 'x'
     case 'i':

llvm/test/CodeGen/X86/mmx-inlineasm.ll

@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx | FileCheck %s
+
+;; Verify that the mmx 'y' constraint works with arbitrary IR types.
+define <2 x i32> @test_mmx_asm(<2 x i32> %a) nounwind {
+; CHECK-LABEL: test_mmx_asm:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movdq2q %xmm0, %mm0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    # %mm0 = %mm0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    # %mm0 = %mm0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movq2dq %mm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = tail call i64 asm sideeffect "# $0 = $1", "=y,y"(<2 x i32> %a)
+  %2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=y,y"(i64 %1)
+  ret <2 x i32> %2
+}
+
+;; And same thing with the 'Ym' constraint.
+define <2 x i32> @test_mmx_asm_Ym(<2 x i32> %a) nounwind {
+; CHECK-LABEL: test_mmx_asm_Ym:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movdq2q %xmm0, %mm0
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    # %mm0 = %mm0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    # %mm0 = %mm0
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    movq2dq %mm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = tail call i64 asm sideeffect "# $0 = $1", "=^Ym,^Ym"(<2 x i32> %a)
+  %2 = tail call <2 x i32> asm sideeffect "# $0 = $1", "=^Ym,^Ym"(i64 %1)
+  ret <2 x i32> %2
+}