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AMDGPU: Work around machine verifier failure with convergence tokens
Apparently any function with convergence tokens will fail the machine verifier after register allocation. The existing codegen tests for tokens use stop-before, and do not run to the end. Work around this by splitting out tests with convergence tokens. Fixes EXPENSIVE_CHECKS bot failures after c08d7b3 and 428ae0f
1 parent b01be72 commit e5a0c30

4 files changed

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-44
lines changed

‎llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.convergencetokens.ll

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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
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; FIXME: Merge with tail-call-inreg-arguments.ll
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; Currently all functions with convergence tokens will fail the
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; machine verifier after register allocation.
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declare void @void_func_i64_inreg(i64 inreg)
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define void @tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens() #0 {
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; CHECK-LABEL: name: tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr6_sgpr7, $vgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr31
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; CHECK-NEXT: [[CONVERGENCECTRL_ENTRY:%[0-9]+]]:sreg_64 = CONVERGENCECTRL_ENTRY
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub1
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub0
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
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; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY11]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
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; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY12]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @void_func_i64_inreg, target-flags(amdgpu-gotprel32-hi) @void_func_i64_inreg, implicit-def dead $scc
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; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:ccr_sgpr_64 = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]]
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; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY1]]
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; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY7]]
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; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY6]]
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; CHECK-NEXT: $sgpr12 = COPY [[COPY5]]
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; CHECK-NEXT: $sgpr13 = COPY [[COPY4]]
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; CHECK-NEXT: $sgpr14 = COPY [[COPY3]]
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; CHECK-NEXT: $sgpr15 = COPY [[COPY2]]
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; CHECK-NEXT: $vgpr31 = COPY [[COPY]]
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; CHECK-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
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; CHECK-NEXT: $sgpr1 = COPY [[V_READFIRSTLANE_B32_1]]
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: SI_TCRETURN killed [[S_LOAD_DWORDX2_IMM]], @void_func_i64_inreg, 0, csr_amdgpu, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit $sgpr0, implicit $sgpr1, implicit [[CONVERGENCECTRL_ENTRY]]
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%t = call token @llvm.experimental.convergence.entry()
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%uniform.vgpr = load i64, ptr addrspace(3) null, align 8
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tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr) #0 [ "convergencectrl"(token %t) ]
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ret void
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}
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attributes #0 = { convergent }

‎llvm/test/CodeGen/AMDGPU/tail-call-inreg-arguments.ll

Lines changed: 1 addition & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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declare hidden void @void_func_i32_inreg(i32 inreg)
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@@ -72,26 +72,3 @@ define void @tail_call_i64_inreg_uniform_in_vgpr() {
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tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr)
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ret void
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}
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define void @tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens() #0 {
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; CHECK-LABEL: tail_call_i64_inreg_uniform_in_vgpr_convergence_tokens:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b64 v[0:1], v0
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; CHECK-NEXT: s_getpc_b64 s[18:19]
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; CHECK-NEXT: s_add_u32 s18, s18, void_func_i64_inreg@gotpcrel32@lo+4
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; CHECK-NEXT: s_addc_u32 s19, s19, void_func_i64_inreg@gotpcrel32@hi+12
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; CHECK-NEXT: s_load_dwordx2 s[18:19], s[18:19], 0x0
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; CHECK-NEXT: ; meta instruction
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: v_readfirstlane_b32 s1, v1
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; CHECK-NEXT: s_setpc_b64 s[18:19]
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%t = call token @llvm.experimental.convergence.entry()
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%uniform.vgpr = load i64, ptr addrspace(3) null, align 8
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tail call void @void_func_i64_inreg(i64 inreg %uniform.vgpr) #0 [ "convergencectrl"(token %t) ]
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ret void
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}
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attributes #0 = { convergent }

‎llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.convergencetokens.ll

Lines changed: 54 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
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; FIXME: This should merge with
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; tail-call-uniform-target-in-vgprs-issue110930.ll. This is split
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; because all functions involving convergence tokens will fail the
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; machine verifier after register allocation.
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target triple = "amdgcn-amd-amdhsa"
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define void @tail_call_uniform_vgpr_value_convergence_tokens() #0 {
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; CHECK-LABEL: name: tail_call_uniform_vgpr_value_convergence_tokens
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: liveins: $sgpr4_sgpr5, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr12, $sgpr13, $sgpr14, $sgpr15, $sgpr6_sgpr7, $vgpr31
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr31
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr15
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr14
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr13
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr12
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK-NEXT: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; CHECK-NEXT: [[CONVERGENCECTRL_ENTRY:%[0-9]+]]:sreg_64 = CONVERGENCECTRL_ENTRY
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s64) from `ptr addrspace(3) null`, addrspace 3)
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; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub1
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY9]]
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; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY10]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[DS_READ_B64_gfx9_]].sub0
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
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; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 killed [[COPY12]], implicit $exec, implicit [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:ccr_sgpr_64 = REG_SEQUENCE killed [[V_READFIRSTLANE_B32_1]], %subreg.sub0, killed [[V_READFIRSTLANE_B32_]], %subreg.sub1
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; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[COPY8]]
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; CHECK-NEXT: $sgpr6_sgpr7 = COPY [[COPY1]]
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; CHECK-NEXT: $sgpr8_sgpr9 = COPY [[COPY7]]
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; CHECK-NEXT: $sgpr10_sgpr11 = COPY [[COPY6]]
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; CHECK-NEXT: $sgpr12 = COPY [[COPY5]]
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; CHECK-NEXT: $sgpr13 = COPY [[COPY4]]
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; CHECK-NEXT: $sgpr14 = COPY [[COPY3]]
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; CHECK-NEXT: $sgpr15 = COPY [[COPY2]]
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; CHECK-NEXT: $vgpr31 = COPY [[COPY]]
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; CHECK-NEXT: CONVERGENCECTRL_GLUE [[CONVERGENCECTRL_ENTRY]]
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; CHECK-NEXT: SI_TCRETURN killed [[REG_SEQUENCE]], 0, 0, csr_amdgpu, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $sgpr15, implicit $vgpr31, implicit [[CONVERGENCECTRL_ENTRY]]
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%t = call token @llvm.experimental.convergence.entry()
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%fptr = load ptr, ptr addrspace(3) null, align 8
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tail call void %fptr() #0 [ "convergencectrl"(token %t) ]
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ret void
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}
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attributes #0 = { convergent }

‎llvm/test/CodeGen/AMDGPU/tail-call-uniform-target-in-vgprs-issue110930.ll

Lines changed: 1 addition & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
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target triple = "amdgcn-amd-amdhsa"
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@@ -37,22 +37,3 @@ define void @tail_call_uniform_sgpr_value() {
3737
tail call void %fptr()
3838
ret void
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}
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define void @tail_call_uniform_vgpr_value_convergence_tokens() #0 {
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; CHECK-LABEL: tail_call_uniform_vgpr_value_convergence_tokens:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: ds_read_b64 v[0:1], v0
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; CHECK-NEXT: ; meta instruction
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s19, v1
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; CHECK-NEXT: v_readfirstlane_b32 s18, v0
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; CHECK-NEXT: s_setpc_b64 s[18:19]
52-
%t = call token @llvm.experimental.convergence.entry()
53-
%fptr = load ptr, ptr addrspace(3) null, align 8
54-
tail call void %fptr() #0 [ "convergencectrl"(token %t) ]
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ret void
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}
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attributes #0 = { convergent }

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