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[RISCV][RFC] Enable store clustering by default
1 parent c9ca21b commit e5eaf0c

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lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,6 +347,7 @@ class RISCVPassConfig : public TargetPassConfig {
347347
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
348348
ScheduleDAGMILive *DAG = createGenericSchedLive(C);
349349
DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI, true));
350+
DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI, true));
350351
if (ST.hasMacroFusion())
351352
DAG->addMutation(createRISCVMacroFusionDAGMutation());
352353
return DAG;

‎llvm/test/CodeGen/RISCV/add-before-shl.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -182,8 +182,8 @@ define i128 @add_wide_operand(i128 %a) nounwind {
182182
; RV32I-NEXT: lui a4, 128
183183
; RV32I-NEXT: add a1, a1, a4
184184
; RV32I-NEXT: sw a2, 0(a0)
185-
; RV32I-NEXT: sw a3, 8(a0)
186185
; RV32I-NEXT: sw a5, 4(a0)
186+
; RV32I-NEXT: sw a3, 8(a0)
187187
; RV32I-NEXT: sw a1, 12(a0)
188188
; RV32I-NEXT: jalr zero, 0(ra)
189189
;
@@ -217,8 +217,8 @@ define i128 @add_wide_operand(i128 %a) nounwind {
217217
; RV32C-NEXT: c.or a1, a3
218218
; RV32C-NEXT: c.slli a6, 3
219219
; RV32C-NEXT: sw a6, 0(a0)
220-
; RV32C-NEXT: c.sw a1, 8(a0)
221220
; RV32C-NEXT: c.sw a4, 4(a0)
221+
; RV32C-NEXT: c.sw a1, 8(a0)
222222
; RV32C-NEXT: c.sw a2, 12(a0)
223223
; RV32C-NEXT: c.jr ra
224224
;

‎llvm/test/CodeGen/RISCV/alloca.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -76,21 +76,21 @@ define void @alloca_callframe(i32 %n) nounwind {
7676
; RV32I-NEXT: sub a0, sp, a0
7777
; RV32I-NEXT: mv sp, a0
7878
; RV32I-NEXT: addi sp, sp, -16
79-
; RV32I-NEXT: li a1, 12
80-
; RV32I-NEXT: sw a1, 12(sp)
81-
; RV32I-NEXT: li a1, 11
82-
; RV32I-NEXT: sw a1, 8(sp)
83-
; RV32I-NEXT: li a1, 10
84-
; RV32I-NEXT: sw a1, 4(sp)
85-
; RV32I-NEXT: li t0, 9
79+
; RV32I-NEXT: li t0, 12
80+
; RV32I-NEXT: li t1, 11
81+
; RV32I-NEXT: li t2, 10
82+
; RV32I-NEXT: li t3, 9
8683
; RV32I-NEXT: li a1, 2
8784
; RV32I-NEXT: li a2, 3
8885
; RV32I-NEXT: li a3, 4
8986
; RV32I-NEXT: li a4, 5
9087
; RV32I-NEXT: li a5, 6
9188
; RV32I-NEXT: li a6, 7
9289
; RV32I-NEXT: li a7, 8
93-
; RV32I-NEXT: sw t0, 0(sp)
90+
; RV32I-NEXT: sw t3, 0(sp)
91+
; RV32I-NEXT: sw t2, 4(sp)
92+
; RV32I-NEXT: sw t1, 8(sp)
93+
; RV32I-NEXT: sw t0, 12(sp)
9494
; RV32I-NEXT: call func@plt
9595
; RV32I-NEXT: addi sp, sp, 16
9696
; RV32I-NEXT: addi sp, s0, -16

‎llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -146,19 +146,19 @@ define void @caller_aligned_stack() nounwind {
146146
; RV32I-FPELIM-NEXT: addi sp, sp, -64
147147
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
148148
; RV32I-FPELIM-NEXT: li a0, 18
149+
; RV32I-FPELIM-NEXT: li a1, 17
150+
; RV32I-FPELIM-NEXT: li a2, 16
151+
; RV32I-FPELIM-NEXT: lui a3, 262236
152+
; RV32I-FPELIM-NEXT: addi a3, a3, 655
153+
; RV32I-FPELIM-NEXT: lui a4, 377487
154+
; RV32I-FPELIM-NEXT: addi a4, a4, 1475
155+
; RV32I-FPELIM-NEXT: li a5, 15
156+
; RV32I-FPELIM-NEXT: sw a5, 0(sp)
157+
; RV32I-FPELIM-NEXT: sw a4, 8(sp)
158+
; RV32I-FPELIM-NEXT: sw a3, 12(sp)
159+
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
160+
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
149161
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
150-
; RV32I-FPELIM-NEXT: li a0, 17
151-
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
152-
; RV32I-FPELIM-NEXT: li a0, 16
153-
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
154-
; RV32I-FPELIM-NEXT: lui a0, 262236
155-
; RV32I-FPELIM-NEXT: addi a0, a0, 655
156-
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
157-
; RV32I-FPELIM-NEXT: lui a0, 377487
158-
; RV32I-FPELIM-NEXT: addi a0, a0, 1475
159-
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
160-
; RV32I-FPELIM-NEXT: li a0, 15
161-
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
162162
; RV32I-FPELIM-NEXT: lui a0, 262153
163163
; RV32I-FPELIM-NEXT: addi a0, a0, 491
164164
; RV32I-FPELIM-NEXT: sw a0, 44(sp)
@@ -192,19 +192,19 @@ define void @caller_aligned_stack() nounwind {
192192
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
193193
; RV32I-WITHFP-NEXT: addi s0, sp, 64
194194
; RV32I-WITHFP-NEXT: li a0, 18
195+
; RV32I-WITHFP-NEXT: li a1, 17
196+
; RV32I-WITHFP-NEXT: li a2, 16
197+
; RV32I-WITHFP-NEXT: lui a3, 262236
198+
; RV32I-WITHFP-NEXT: addi a3, a3, 655
199+
; RV32I-WITHFP-NEXT: lui a4, 377487
200+
; RV32I-WITHFP-NEXT: addi a4, a4, 1475
201+
; RV32I-WITHFP-NEXT: li a5, 15
202+
; RV32I-WITHFP-NEXT: sw a5, 0(sp)
203+
; RV32I-WITHFP-NEXT: sw a4, 8(sp)
204+
; RV32I-WITHFP-NEXT: sw a3, 12(sp)
205+
; RV32I-WITHFP-NEXT: sw a2, 16(sp)
206+
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
195207
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
196-
; RV32I-WITHFP-NEXT: li a0, 17
197-
; RV32I-WITHFP-NEXT: sw a0, 20(sp)
198-
; RV32I-WITHFP-NEXT: li a0, 16
199-
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
200-
; RV32I-WITHFP-NEXT: lui a0, 262236
201-
; RV32I-WITHFP-NEXT: addi a0, a0, 655
202-
; RV32I-WITHFP-NEXT: sw a0, 12(sp)
203-
; RV32I-WITHFP-NEXT: lui a0, 377487
204-
; RV32I-WITHFP-NEXT: addi a0, a0, 1475
205-
; RV32I-WITHFP-NEXT: sw a0, 8(sp)
206-
; RV32I-WITHFP-NEXT: li a0, 15
207-
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
208208
; RV32I-WITHFP-NEXT: lui a0, 262153
209209
; RV32I-WITHFP-NEXT: addi a0, a0, 491
210210
; RV32I-WITHFP-NEXT: sw a0, -20(s0)

‎llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,7 @@ define i32 @caller_many_scalars() nounwind {
142142
; RV32I-FPELIM: # %bb.0:
143143
; RV32I-FPELIM-NEXT: addi sp, sp, -16
144144
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
145-
; RV32I-FPELIM-NEXT: li a0, 8
146-
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
145+
; RV32I-FPELIM-NEXT: li a4, 8
147146
; RV32I-FPELIM-NEXT: li a0, 1
148147
; RV32I-FPELIM-NEXT: li a1, 2
149148
; RV32I-FPELIM-NEXT: li a2, 3
@@ -152,6 +151,7 @@ define i32 @caller_many_scalars() nounwind {
152151
; RV32I-FPELIM-NEXT: li a6, 6
153152
; RV32I-FPELIM-NEXT: li a7, 7
154153
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
154+
; RV32I-FPELIM-NEXT: sw a4, 4(sp)
155155
; RV32I-FPELIM-NEXT: li a4, 0
156156
; RV32I-FPELIM-NEXT: call callee_many_scalars@plt
157157
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -164,8 +164,7 @@ define i32 @caller_many_scalars() nounwind {
164164
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
165165
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
166166
; RV32I-WITHFP-NEXT: addi s0, sp, 16
167-
; RV32I-WITHFP-NEXT: li a0, 8
168-
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
167+
; RV32I-WITHFP-NEXT: li a4, 8
169168
; RV32I-WITHFP-NEXT: li a0, 1
170169
; RV32I-WITHFP-NEXT: li a1, 2
171170
; RV32I-WITHFP-NEXT: li a2, 3
@@ -174,6 +173,7 @@ define i32 @caller_many_scalars() nounwind {
174173
; RV32I-WITHFP-NEXT: li a6, 6
175174
; RV32I-WITHFP-NEXT: li a7, 7
176175
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
176+
; RV32I-WITHFP-NEXT: sw a4, 4(sp)
177177
; RV32I-WITHFP-NEXT: li a4, 0
178178
; RV32I-WITHFP-NEXT: call callee_many_scalars@plt
179179
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -354,9 +354,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
354354
; RV32I-FPELIM-NEXT: addi sp, sp, -64
355355
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
356356
; RV32I-FPELIM-NEXT: addi a0, sp, 16
357+
; RV32I-FPELIM-NEXT: li a1, 9
358+
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
357359
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
358-
; RV32I-FPELIM-NEXT: li a0, 9
359-
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
360360
; RV32I-FPELIM-NEXT: lui a0, 524272
361361
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
362362
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
@@ -387,9 +387,9 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
387387
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
388388
; RV32I-WITHFP-NEXT: addi s0, sp, 64
389389
; RV32I-WITHFP-NEXT: addi a0, s0, -48
390+
; RV32I-WITHFP-NEXT: li a1, 9
391+
; RV32I-WITHFP-NEXT: sw a1, 0(sp)
390392
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
391-
; RV32I-WITHFP-NEXT: li a0, 9
392-
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
393393
; RV32I-WITHFP-NEXT: lui a0, 524272
394394
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
395395
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
@@ -665,16 +665,16 @@ define void @caller_aligned_stack() nounwind {
665665
; RV32I-FPELIM-NEXT: addi sp, sp, -64
666666
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
667667
; RV32I-FPELIM-NEXT: li a0, 19
668-
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
669-
; RV32I-FPELIM-NEXT: li a0, 18
670-
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
671-
; RV32I-FPELIM-NEXT: li a0, 17
672-
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
668+
; RV32I-FPELIM-NEXT: li a1, 18
669+
; RV32I-FPELIM-NEXT: li a2, 17
670+
; RV32I-FPELIM-NEXT: li a3, 16
671+
; RV32I-FPELIM-NEXT: li a4, 15
672+
; RV32I-FPELIM-NEXT: sw a4, 0(sp)
673+
; RV32I-FPELIM-NEXT: sw a3, 8(sp)
673674
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
674-
; RV32I-FPELIM-NEXT: li a0, 16
675-
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
676-
; RV32I-FPELIM-NEXT: li a0, 15
677-
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
675+
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
676+
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
677+
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
678678
; RV32I-FPELIM-NEXT: lui a0, 262153
679679
; RV32I-FPELIM-NEXT: addi a0, a0, 491
680680
; RV32I-FPELIM-NEXT: sw a0, 44(sp)
@@ -708,16 +708,16 @@ define void @caller_aligned_stack() nounwind {
708708
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
709709
; RV32I-WITHFP-NEXT: addi s0, sp, 64
710710
; RV32I-WITHFP-NEXT: li a0, 19
711-
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
712-
; RV32I-WITHFP-NEXT: li a0, 18
713-
; RV32I-WITHFP-NEXT: sw a0, 20(sp)
714-
; RV32I-WITHFP-NEXT: li a0, 17
715-
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
711+
; RV32I-WITHFP-NEXT: li a1, 18
712+
; RV32I-WITHFP-NEXT: li a2, 17
713+
; RV32I-WITHFP-NEXT: li a3, 16
714+
; RV32I-WITHFP-NEXT: li a4, 15
715+
; RV32I-WITHFP-NEXT: sw a4, 0(sp)
716+
; RV32I-WITHFP-NEXT: sw a3, 8(sp)
716717
; RV32I-WITHFP-NEXT: sw zero, 12(sp)
717-
; RV32I-WITHFP-NEXT: li a0, 16
718-
; RV32I-WITHFP-NEXT: sw a0, 8(sp)
719-
; RV32I-WITHFP-NEXT: li a0, 15
720-
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
718+
; RV32I-WITHFP-NEXT: sw a2, 16(sp)
719+
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
720+
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
721721
; RV32I-WITHFP-NEXT: lui a0, 262153
722722
; RV32I-WITHFP-NEXT: addi a0, a0, 491
723723
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
@@ -881,10 +881,10 @@ define fp128 @callee_large_scalar_ret() nounwind {
881881
; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
882882
; RV32I-FPELIM: # %bb.0:
883883
; RV32I-FPELIM-NEXT: lui a1, 524272
884-
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
885-
; RV32I-FPELIM-NEXT: sw zero, 8(a0)
886-
; RV32I-FPELIM-NEXT: sw zero, 4(a0)
887884
; RV32I-FPELIM-NEXT: sw zero, 0(a0)
885+
; RV32I-FPELIM-NEXT: sw zero, 4(a0)
886+
; RV32I-FPELIM-NEXT: sw zero, 8(a0)
887+
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
888888
; RV32I-FPELIM-NEXT: ret
889889
;
890890
; RV32I-WITHFP-LABEL: callee_large_scalar_ret:
@@ -894,10 +894,10 @@ define fp128 @callee_large_scalar_ret() nounwind {
894894
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
895895
; RV32I-WITHFP-NEXT: addi s0, sp, 16
896896
; RV32I-WITHFP-NEXT: lui a1, 524272
897-
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
898-
; RV32I-WITHFP-NEXT: sw zero, 8(a0)
899-
; RV32I-WITHFP-NEXT: sw zero, 4(a0)
900897
; RV32I-WITHFP-NEXT: sw zero, 0(a0)
898+
; RV32I-WITHFP-NEXT: sw zero, 4(a0)
899+
; RV32I-WITHFP-NEXT: sw zero, 8(a0)
900+
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
901901
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
902902
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
903903
; RV32I-WITHFP-NEXT: addi sp, sp, 16
@@ -938,13 +938,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
938938
; RV32I-FPELIM-LABEL: callee_large_struct_ret:
939939
; RV32I-FPELIM: # %bb.0:
940940
; RV32I-FPELIM-NEXT: li a1, 1
941+
; RV32I-FPELIM-NEXT: li a2, 2
942+
; RV32I-FPELIM-NEXT: li a3, 3
943+
; RV32I-FPELIM-NEXT: li a4, 4
941944
; RV32I-FPELIM-NEXT: sw a1, 0(a0)
942-
; RV32I-FPELIM-NEXT: li a1, 2
943-
; RV32I-FPELIM-NEXT: sw a1, 4(a0)
944-
; RV32I-FPELIM-NEXT: li a1, 3
945-
; RV32I-FPELIM-NEXT: sw a1, 8(a0)
946-
; RV32I-FPELIM-NEXT: li a1, 4
947-
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
945+
; RV32I-FPELIM-NEXT: sw a2, 4(a0)
946+
; RV32I-FPELIM-NEXT: sw a3, 8(a0)
947+
; RV32I-FPELIM-NEXT: sw a4, 12(a0)
948948
; RV32I-FPELIM-NEXT: ret
949949
;
950950
; RV32I-WITHFP-LABEL: callee_large_struct_ret:
@@ -954,13 +954,13 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
954954
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
955955
; RV32I-WITHFP-NEXT: addi s0, sp, 16
956956
; RV32I-WITHFP-NEXT: li a1, 1
957+
; RV32I-WITHFP-NEXT: li a2, 2
958+
; RV32I-WITHFP-NEXT: li a3, 3
959+
; RV32I-WITHFP-NEXT: li a4, 4
957960
; RV32I-WITHFP-NEXT: sw a1, 0(a0)
958-
; RV32I-WITHFP-NEXT: li a1, 2
959-
; RV32I-WITHFP-NEXT: sw a1, 4(a0)
960-
; RV32I-WITHFP-NEXT: li a1, 3
961-
; RV32I-WITHFP-NEXT: sw a1, 8(a0)
962-
; RV32I-WITHFP-NEXT: li a1, 4
963-
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
961+
; RV32I-WITHFP-NEXT: sw a2, 4(a0)
962+
; RV32I-WITHFP-NEXT: sw a3, 8(a0)
963+
; RV32I-WITHFP-NEXT: sw a4, 12(a0)
964964
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
965965
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
966966
; RV32I-WITHFP-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -203,8 +203,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
203203
; RV32-ILP32D: # %bb.0:
204204
; RV32-ILP32D-NEXT: addi sp, sp, -16
205205
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
206-
; RV32-ILP32D-NEXT: lui a0, 262816
207-
; RV32-ILP32D-NEXT: sw a0, 4(sp)
206+
; RV32-ILP32D-NEXT: lui a1, 262816
208207
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
209208
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0)
210209
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
@@ -226,6 +225,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
226225
; RV32-ILP32D-NEXT: li a4, 5
227226
; RV32-ILP32D-NEXT: li a6, 7
228227
; RV32-ILP32D-NEXT: sw zero, 0(sp)
228+
; RV32-ILP32D-NEXT: sw a1, 4(sp)
229229
; RV32-ILP32D-NEXT: li a1, 0
230230
; RV32-ILP32D-NEXT: li a3, 0
231231
; RV32-ILP32D-NEXT: li a5, 0

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