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YonahGoldbergYonahGoldberg
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Merge branch 'main' into nvvm-reflect
2 parents 47f280e + 80267f8 commit e61755d

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‎clang/lib/Basic/Targets/SystemZ.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ static constexpr ISANameRevision ISARevisions[] = {
114114
{{"arch12"}, 12}, {{"z14"}, 12},
115115
{{"arch13"}, 13}, {{"z15"}, 13},
116116
{{"arch14"}, 14}, {{"z16"}, 14},
117-
{{"arch15"}, 15},
117+
{{"arch15"}, 15}, {{"z17"}, 15},
118118
};
119119

120120
int SystemZTargetInfo::getISARevision(StringRef Name) const {

‎clang/test/CodeGen/SystemZ/builtins-systemz-bitop.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// REQUIRES: systemz-registered-target
2-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
3-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
2+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
3+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -Wall -Wno-unused -Werror -emit-llvm -x c++ %s -o - | FileCheck %s
44

55
unsigned long test_bdepg(unsigned long a, unsigned long b) {
66
// CHECK-LABEL: test_bdepg

‎clang/test/CodeGen/SystemZ/builtins-systemz-vector5-error.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// REQUIRES: systemz-registered-target
2-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-unknown-unknown \
2+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-unknown-unknown \
33
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s
44

55
typedef __attribute__((vector_size(16))) signed char vec_schar;

‎clang/test/CodeGen/SystemZ/builtins-systemz-vector5.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// REQUIRES: systemz-registered-target
2-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-ibm-linux -flax-vector-conversions=none \
2+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-ibm-linux -flax-vector-conversions=none \
33
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
44

55
typedef __attribute__((vector_size(16))) signed char vec_schar;

‎clang/test/CodeGen/SystemZ/builtins-systemz-zvector5-error.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// REQUIRES: systemz-registered-target
2-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
2+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
33
// RUN: -fzvector -flax-vector-conversions=none \
44
// RUN: -Wall -Wno-unused -Werror -fsyntax-only -verify %s
55

‎clang/test/CodeGen/SystemZ/builtins-systemz-zvector5.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// REQUIRES: systemz-registered-target
2-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
2+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
33
// RUN: -O2 -fzvector -flax-vector-conversions=none \
44
// RUN: -Wall -Wno-unused -Werror -emit-llvm %s -o - | FileCheck %s
5-
// RUN: %clang_cc1 -target-cpu arch15 -triple s390x-linux-gnu \
5+
// RUN: %clang_cc1 -target-cpu z17 -triple s390x-linux-gnu \
66
// RUN: -O2 -fzvector -flax-vector-conversions=none \
77
// RUN: -Wall -Wno-unused -Werror -S %s -o - | FileCheck %s --check-prefix=CHECK-ASM
88

‎clang/test/CodeGen/SystemZ/systemz-abi-vector.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@
1818
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
1919
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
2020
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
21+
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
22+
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
2123
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
2224
// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-VECTOR %s
2325

‎clang/test/CodeGen/SystemZ/systemz-abi.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@
2424
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch14 \
2525
// RUN: -emit-llvm -o - %s -mfloat-abi soft | FileCheck %s \
2626
// RUN: --check-prefixes=CHECK,SOFT-FLOAT
27+
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu z17 \
28+
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
2729
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \
2830
// RUN: -emit-llvm -o - %s | FileCheck %s --check-prefixes=CHECK,HARD-FLOAT
2931
// RUN: %clang_cc1 -no-enable-noundef-analysis -triple s390x-linux-gnu -target-cpu arch15 \

‎clang/test/Driver/systemz-march.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch13 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH13 %s
1616
// RUN: %clang -target s390x -### -S -emit-llvm -march=z16 %s 2>&1 | FileCheck --check-prefix=CHECK-Z16 %s
1717
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch14 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH14 %s
18+
// RUN: %clang -target s390x -### -S -emit-llvm -march=z17 %s 2>&1 | FileCheck --check-prefix=CHECK-Z17 %s
1819
// RUN: %clang -target s390x -### -S -emit-llvm -march=arch15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH15 %s
1920

2021
// CHECK-Z9: error: unknown target CPU 'z9'
@@ -32,6 +33,7 @@
3233
// CHECK-ARCH13: "-target-cpu" "arch13"
3334
// CHECK-Z16: "-target-cpu" "z16"
3435
// CHECK-ARCH14: "-target-cpu" "arch14"
36+
// CHECK-Z17: "-target-cpu" "z17"
3537
// CHECK-ARCH15: "-target-cpu" "arch15"
3638

3739
int x;

‎clang/test/Misc/target-invalid-cpu-note/systemz.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,4 +20,5 @@
2020
// CHECK-SAME: {{^}}, arch14
2121
// CHECK-SAME: {{^}}, z16
2222
// CHECK-SAME: {{^}}, arch15
23+
// CHECK-SAME: {{^}}, z17
2324
// CHECK-SAME: {{$}}

‎clang/test/Preprocessor/predefined-arch-macros.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4394,6 +4394,9 @@
43944394
// RUN: %clang -march=arch15 -E -dM %s -o - 2>&1 \
43954395
// RUN: -target s390x-unknown-linux \
43964396
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
4397+
// RUN: %clang -march=z17 -E -dM %s -o - 2>&1 \
4398+
// RUN: -target s390x-unknown-linux \
4399+
// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ARCH15
43974400
// CHECK_SYSTEMZ_ARCH15: #define __ARCH__ 15
43984401
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
43994402
// CHECK_SYSTEMZ_ARCH15: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1

‎compiler-rt/lib/asan/asan_poisoning.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -161,10 +161,11 @@ void __asan_poison_memory_region(void const volatile *addr, uptr size) {
161161

162162
u32 stack_id = StackDepotPut(stack);
163163

164-
PoisonRecord record{.stack_id = stack_id,
165-
.thread_id = current_tid,
166-
.begin = beg_addr,
167-
.end = end_addr};
164+
PoisonRecord record;
165+
record.stack_id = stack_id;
166+
record.thread_id = current_tid;
167+
record.begin = beg_addr;
168+
record.end = end_addr;
168169
AddPoisonRecord(record);
169170
}
170171

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
258258
setOperationAction(ISD::FSHL, MVT::i128, Custom);
259259
setOperationAction(ISD::FSHR, MVT::i128, Custom);
260260

261-
// No special instructions for these before arch15.
261+
// No special instructions for these before z17.
262262
if (!Subtarget.hasVectorEnhancements3()) {
263263
setOperationAction(ISD::MUL, MVT::i128, Expand);
264264
setOperationAction(ISD::MULHS, MVT::i128, Expand);
@@ -285,7 +285,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
285285
// Use VPOPCT and add up partial results.
286286
setOperationAction(ISD::CTPOP, MVT::i128, Custom);
287287

288-
// Additional instructions available with arch15.
288+
// Additional instructions available with z17.
289289
if (Subtarget.hasVectorEnhancements3()) {
290290
setOperationAction(ISD::ABS, MVT::i128, Legal);
291291
}
@@ -357,7 +357,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
357357
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Promote);
358358
setOperationAction(ISD::CTLZ, MVT::i64, Legal);
359359

360-
// On arch15 we have native support for a 64-bit CTTZ.
360+
// On z17 we have native support for a 64-bit CTTZ.
361361
if (Subtarget.hasMiscellaneousExtensions4()) {
362362
setOperationAction(ISD::CTTZ, MVT::i32, Promote);
363363
setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Promote);
@@ -4526,7 +4526,7 @@ SDValue SystemZTargetLowering::lowerMULH(SDValue Op,
45264526
SDLoc DL(Op);
45274527
SDValue Even, Odd;
45284528

4529-
// This custom expander is only used on arch15 and later for 64-bit types.
4529+
// This custom expander is only used on z17 and later for 64-bit types.
45304530
assert(!is32Bit(VT));
45314531
assert(Subtarget.hasMiscellaneousExtensions2());
45324532

@@ -8733,7 +8733,7 @@ static unsigned detectEvenOddMultiplyOperand(const SelectionDAG &DAG,
87338733
}
87348734
}
87358735

8736-
// For arch15, we can also support the v2i64->i128 case, which looks like
8736+
// For z17, we can also support the v2i64->i128 case, which looks like
87378737
// (sign/zero_extend (extract_vector_elt X 0/1))
87388738
if (VT == MVT::i128 && Subtarget.hasVectorEnhancements3() &&
87398739
(Op.getOpcode() == ISD::SIGN_EXTEND ||

‎llvm/lib/Target/SystemZ/SystemZInstrVector.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1995,7 +1995,7 @@ let Predicates = [FeatureVector] in {
19951995
(VLEG (VGBM 0), bdxaddr12only:$addr, 1)>;
19961996
}
19971997

1998-
// Zero-extensions from VR element to i128 on arch15.
1998+
// Zero-extensions from VR element to i128 on z17.
19991999
let Predicates = [FeatureVectorEnhancements3] in {
20002000
def : Pat<(i128 (zext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
20012001
(VUPLHG VR128:$src)>;
@@ -2011,7 +2011,7 @@ let Predicates = [FeatureVectorEnhancements3] in {
20112011
(VUPLLG (VUPLLF VR128:$src))>;
20122012
}
20132013

2014-
// In-register i128 sign-extensions on arch15.
2014+
// In-register i128 sign-extensions on z17.
20152015
let Predicates = [FeatureVectorEnhancements3] in {
20162016
def : Pat<(i128 (sext_inreg VR128:$x, i8)), (VUPLG (VSEGB VR128:$x))>;
20172017
def : Pat<(i128 (sext_inreg VR128:$x, i16)), (VUPLG (VSEGH VR128:$x))>;
@@ -2031,7 +2031,7 @@ let Predicates = [FeatureVector] in {
20312031
(VSRAB (VREPG VR128:$x, 1), (VREPIB 64))>;
20322032
}
20332033

2034-
// Sign-extensions from GPR to i128 on arch15.
2034+
// Sign-extensions from GPR to i128 on z17.
20352035
let Predicates = [FeatureVectorEnhancements3] in {
20362036
def : Pat<(i128 (sext_inreg (anyext GR32:$x), i8)),
20372037
(VUPLG (VLVGP (LGBR (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$x, subreg_l32)),
@@ -2075,7 +2075,7 @@ let Predicates = [FeatureVector] in {
20752075
(VSRAB (VLREPG bdxaddr12only:$addr), (VREPIB 64))>;
20762076
}
20772077

2078-
// Sign-extensions from VR element to i128 on arch15.
2078+
// Sign-extensions from VR element to i128 on z17.
20792079
let Predicates = [FeatureVectorEnhancements3] in {
20802080
def : Pat<(i128 (sext (i64 (z_vector_extract (v2i64 VR128:$src), 0)))),
20812081
(VUPHG VR128:$src)>;

‎llvm/lib/Target/SystemZ/SystemZProcessors.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,4 +41,5 @@ def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
4141
def : ProcessorModel<"arch14", Z16Model, Arch14SupportedFeatures.List>;
4242
def : ProcessorModel<"z16", Z16Model, Arch14SupportedFeatures.List>;
4343

44-
def : ProcessorModel<"arch15", Z16Model, Arch15SupportedFeatures.List>;
44+
def : ProcessorModel<"arch15", Z17Model, Arch15SupportedFeatures.List>;
45+
def : ProcessorModel<"z17", Z17Model, Arch15SupportedFeatures.List>;

‎llvm/lib/Target/SystemZ/SystemZSchedule.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ def VBU : SchedWrite; // Virtual branching unit
6060

6161
def MCD : SchedWrite; // Millicode
6262

63+
include "SystemZScheduleZ17.td"
6364
include "SystemZScheduleZ16.td"
6465
include "SystemZScheduleZ15.td"
6566
include "SystemZScheduleZ14.td"

‎llvm/lib/Target/SystemZ/SystemZScheduleZ16.td

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1555,12 +1555,12 @@ def : InstRW<[WLat2, VecDFX, NormalGr], (instregex "V(T|C)P$")>;
15551555

15561556
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCH(S|D|X)?P$")>;
15571557
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VSCSHP$")>;
1558-
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH")>;
1559-
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP")>;
1560-
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR")>;
1561-
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR")>;
1562-
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH")>;
1563-
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL")>;
1558+
def : InstRW<[WLat30, VecDF2, NormalGr], (instregex "VCSPH$")>;
1559+
def : InstRW<[WLat2, WLat2, VecXsPm, NormalGr], (instregex "VCLZDP$")>;
1560+
def : InstRW<[WLat10, WLat10, VecDF2, NormalGr], (instregex "VSRPR$")>;
1561+
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VPKZR$")>;
1562+
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZH$")>;
1563+
def : InstRW<[WLat2, WLat2, VecDFX, NormalGr], (instregex "VUPKZL$")>;
15641564

15651565
// -------------------------------- System ---------------------------------- //
15661566

@@ -1597,8 +1597,8 @@ def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
15971597
// System: Breaking-Event-Address-Register Instructions
15981598
//===----------------------------------------------------------------------===//
15991599

1600-
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR")>;
1601-
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR")>;
1600+
def : InstRW<[WLat3LSU, LSU2, GroupAlone], (instregex "LBEAR$")>;
1601+
def : InstRW<[WLat1, LSU2, FXb, GroupAlone], (instregex "STBEAR$")>;
16021602

16031603
//===----------------------------------------------------------------------===//
16041604
// System: Storage-Key and Real Memory Instructions

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