[RISCV] Move the RISCVSchedule.td include after RISCVRegisterInfo.td. NFC

topperc · topperc · commit e64e15ee5973 · 2024-03-22T11:42:12.000-07:00
Registers shouldn't depend on the scheduler, but a scheduler
predicate could depend on a register.

This would make it possible to move VLDSX0Pred out of the SiFive7
scheduler model to RISCVSchedule.td if another model needed it.
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -24,8 +24,8 @@ include "RISCVSystemOperands.td"
 // Registers, calling conventions, instruction descriptions.
 //===----------------------------------------------------------------------===//
 
-include "RISCVSchedule.td"
 include "RISCVRegisterInfo.td"
+include "RISCVSchedule.td"
 include "RISCVCallingConv.td"
 include "RISCVInstrInfo.td"
 include "GISel/RISCVRegisterBanks.td"
