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[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelect
Same with (select C, X, -1), (select C, 0, X), and (select C, X, 0). There's a DAGCombine after we turn the select into select_cc, but that may introduce a setcc that didn't previously exist. We could add more DAGCombines to remove the extra setcc, but this seemed lower effort. Reviewed By: reames Differential Revision: https://reviews.llvm.org/D135833
1 parent e7e3248 commit e68b0d5

18 files changed

+1036
-1250
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4222,6 +4222,30 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
42224222
return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
42234223
}
42244224

4225+
// (select c, -1, y) -> -c | y
4226+
if (isAllOnesConstant(TrueV)) {
4227+
SDValue Neg = DAG.getNegative(CondV, DL, VT);
4228+
return DAG.getNode(ISD::OR, DL, VT, Neg, FalseV);
4229+
}
4230+
// (select c, y, -1) -> (c-1) | y
4231+
if (isAllOnesConstant(FalseV)) {
4232+
SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,
4233+
DAG.getAllOnesConstant(DL, VT));
4234+
return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV);
4235+
}
4236+
4237+
// (select c, 0, y) -> (c-1) & y
4238+
if (isNullConstant(TrueV)) {
4239+
SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,
4240+
DAG.getAllOnesConstant(DL, VT));
4241+
return DAG.getNode(ISD::AND, DL, VT, Neg, FalseV);
4242+
}
4243+
// (select c, y, 0) -> -c & y
4244+
if (isNullConstant(FalseV)) {
4245+
SDValue Neg = DAG.getNegative(CondV, DL, VT);
4246+
return DAG.getNode(ISD::AND, DL, VT, Neg, TrueV);
4247+
}
4248+
42254249
// If the CondV is the output of a SETCC node which operates on XLenVT inputs,
42264250
// then merge the SETCC node into the lowered RISCVISD::SELECT_CC to take
42274251
// advantage of the integer compare+branch instructions. i.e.:

‎llvm/test/CodeGen/RISCV/double-convert.ll

Lines changed: 110 additions & 129 deletions
Original file line numberDiff line numberDiff line change
@@ -309,29 +309,27 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
309309
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
310310
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
311311
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
312-
; RV32I-NEXT: mv s2, a1
313-
; RV32I-NEXT: mv s3, a0
312+
; RV32I-NEXT: mv s0, a1
313+
; RV32I-NEXT: mv s1, a0
314314
; RV32I-NEXT: lui a0, 270080
315315
; RV32I-NEXT: addi a3, a0, -1
316316
; RV32I-NEXT: lui a2, 1048064
317-
; RV32I-NEXT: mv a0, s3
317+
; RV32I-NEXT: mv a0, s1
318318
; RV32I-NEXT: call __gtdf2@plt
319319
; RV32I-NEXT: sgtz a0, a0
320-
; RV32I-NEXT: neg s0, a0
321-
; RV32I-NEXT: mv a0, s3
322-
; RV32I-NEXT: mv a1, s2
323-
; RV32I-NEXT: call __fixunsdfsi@plt
324-
; RV32I-NEXT: mv s1, a0
325-
; RV32I-NEXT: mv a0, s3
326-
; RV32I-NEXT: mv a1, s2
320+
; RV32I-NEXT: neg s2, a0
321+
; RV32I-NEXT: mv a0, s1
322+
; RV32I-NEXT: mv a1, s0
327323
; RV32I-NEXT: li a2, 0
328324
; RV32I-NEXT: li a3, 0
329325
; RV32I-NEXT: call __gedf2@plt
330-
; RV32I-NEXT: bltz a0, .LBB6_2
331-
; RV32I-NEXT: # %bb.1: # %start
332-
; RV32I-NEXT: or s0, s0, s1
333-
; RV32I-NEXT: .LBB6_2: # %start
334-
; RV32I-NEXT: mv a0, s0
326+
; RV32I-NEXT: slti a0, a0, 0
327+
; RV32I-NEXT: addi s3, a0, -1
328+
; RV32I-NEXT: mv a0, s1
329+
; RV32I-NEXT: mv a1, s0
330+
; RV32I-NEXT: call __fixunsdfsi@plt
331+
; RV32I-NEXT: and a0, s3, a0
332+
; RV32I-NEXT: or a0, s2, a0
335333
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
336334
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
337335
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@@ -570,11 +568,9 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
570568
; RV32IFD-NEXT: seqz a3, a3
571569
; RV32IFD-NEXT: addi a3, a3, -1
572570
; RV32IFD-NEXT: and a1, a3, a1
573-
; RV32IFD-NEXT: seqz a4, s0
574-
; RV32IFD-NEXT: addi a4, a4, -1
571+
; RV32IFD-NEXT: neg a2, a2
572+
; RV32IFD-NEXT: neg a4, s0
575573
; RV32IFD-NEXT: and a0, a4, a0
576-
; RV32IFD-NEXT: seqz a2, a2
577-
; RV32IFD-NEXT: addi a2, a2, -1
578574
; RV32IFD-NEXT: or a0, a2, a0
579575
; RV32IFD-NEXT: and a0, a3, a0
580576
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -594,25 +590,24 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
594590
;
595591
; RV32I-LABEL: fcvt_l_d_sat:
596592
; RV32I: # %bb.0: # %start
597-
; RV32I-NEXT: addi sp, sp, -48
598-
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
599-
; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
600-
; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
601-
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
602-
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
603-
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
604-
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
605-
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
606-
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
593+
; RV32I-NEXT: addi sp, sp, -32
594+
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
595+
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
596+
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
597+
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
598+
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
599+
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
600+
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
601+
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
607602
; RV32I-NEXT: mv s0, a1
608603
; RV32I-NEXT: mv s1, a0
609604
; RV32I-NEXT: lui a0, 278016
610-
; RV32I-NEXT: addi s3, a0, -1
605+
; RV32I-NEXT: addi s2, a0, -1
611606
; RV32I-NEXT: li a2, -1
612607
; RV32I-NEXT: mv a0, s1
613-
; RV32I-NEXT: mv a3, s3
608+
; RV32I-NEXT: mv a3, s2
614609
; RV32I-NEXT: call __gtdf2@plt
615-
; RV32I-NEXT: mv s7, a0
610+
; RV32I-NEXT: mv s4, a0
616611
; RV32I-NEXT: lui a3, 802304
617612
; RV32I-NEXT: mv a0, s1
618613
; RV32I-NEXT: mv a1, s0
@@ -622,62 +617,59 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
622617
; RV32I-NEXT: mv a0, s1
623618
; RV32I-NEXT: mv a1, s0
624619
; RV32I-NEXT: call __fixdfdi@plt
625-
; RV32I-NEXT: mv s6, a0
626-
; RV32I-NEXT: mv s4, a1
620+
; RV32I-NEXT: mv s3, a0
621+
; RV32I-NEXT: lui a0, 524288
622+
; RV32I-NEXT: lui s6, 524288
623+
; RV32I-NEXT: bltz s5, .LBB12_2
624+
; RV32I-NEXT: # %bb.1: # %start
625+
; RV32I-NEXT: mv s6, a1
626+
; RV32I-NEXT: .LBB12_2: # %start
627+
; RV32I-NEXT: blez s4, .LBB12_4
628+
; RV32I-NEXT: # %bb.3:
629+
; RV32I-NEXT: addi s6, a0, -1
630+
; RV32I-NEXT: .LBB12_4: # %start
627631
; RV32I-NEXT: mv a0, s1
628632
; RV32I-NEXT: mv a1, s0
629633
; RV32I-NEXT: mv a2, s1
630634
; RV32I-NEXT: mv a3, s0
631635
; RV32I-NEXT: call __unorddf2@plt
632636
; RV32I-NEXT: snez a0, a0
633-
; RV32I-NEXT: addi s2, a0, -1
634-
; RV32I-NEXT: bgtz s7, .LBB12_2
635-
; RV32I-NEXT: # %bb.1: # %start
636-
; RV32I-NEXT: slti a0, s5, 0
637637
; RV32I-NEXT: addi a0, a0, -1
638-
; RV32I-NEXT: and a0, a0, s6
639-
; RV32I-NEXT: and s2, s2, a0
640-
; RV32I-NEXT: .LBB12_2: # %start
641-
; RV32I-NEXT: li a2, -1
642-
; RV32I-NEXT: mv a0, s1
643-
; RV32I-NEXT: mv a1, s0
644-
; RV32I-NEXT: mv a3, s3
645-
; RV32I-NEXT: call __gtdf2@plt
646-
; RV32I-NEXT: mv s3, a0
638+
; RV32I-NEXT: and s4, a0, s6
647639
; RV32I-NEXT: lui a3, 802304
648640
; RV32I-NEXT: mv a0, s1
649641
; RV32I-NEXT: mv a1, s0
650642
; RV32I-NEXT: li a2, 0
651643
; RV32I-NEXT: call __gedf2@plt
652-
; RV32I-NEXT: lui a1, 524288
653-
; RV32I-NEXT: lui s5, 524288
654-
; RV32I-NEXT: bltz a0, .LBB12_4
655-
; RV32I-NEXT: # %bb.3: # %start
656-
; RV32I-NEXT: mv s5, s4
657-
; RV32I-NEXT: .LBB12_4: # %start
658-
; RV32I-NEXT: blez s3, .LBB12_6
659-
; RV32I-NEXT: # %bb.5:
660-
; RV32I-NEXT: addi s5, a1, -1
661-
; RV32I-NEXT: .LBB12_6: # %start
644+
; RV32I-NEXT: slti a0, a0, 0
645+
; RV32I-NEXT: addi a0, a0, -1
646+
; RV32I-NEXT: and s3, a0, s3
647+
; RV32I-NEXT: li a2, -1
648+
; RV32I-NEXT: mv a0, s1
649+
; RV32I-NEXT: mv a1, s0
650+
; RV32I-NEXT: mv a3, s2
651+
; RV32I-NEXT: call __gtdf2@plt
652+
; RV32I-NEXT: sgtz a0, a0
653+
; RV32I-NEXT: neg a0, a0
654+
; RV32I-NEXT: or s2, a0, s3
662655
; RV32I-NEXT: mv a0, s1
663656
; RV32I-NEXT: mv a1, s0
664657
; RV32I-NEXT: mv a2, s1
665658
; RV32I-NEXT: mv a3, s0
666659
; RV32I-NEXT: call __unorddf2@plt
667660
; RV32I-NEXT: snez a0, a0
668661
; RV32I-NEXT: addi a0, a0, -1
669-
; RV32I-NEXT: and a1, a0, s5
670-
; RV32I-NEXT: mv a0, s2
671-
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
672-
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
673-
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
674-
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
675-
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
676-
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
677-
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
678-
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
679-
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
680-
; RV32I-NEXT: addi sp, sp, 48
662+
; RV32I-NEXT: and a0, a0, s2
663+
; RV32I-NEXT: mv a1, s4
664+
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
665+
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
666+
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
667+
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
668+
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
669+
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
670+
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
671+
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
672+
; RV32I-NEXT: addi sp, sp, 32
681673
; RV32I-NEXT: ret
682674
;
683675
; RV64I-LABEL: fcvt_l_d_sat:
@@ -778,15 +770,13 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
778770
; RV32IFD-NEXT: fmv.d fs0, fa0
779771
; RV32IFD-NEXT: fcvt.d.w ft0, zero
780772
; RV32IFD-NEXT: fle.d a0, ft0, fa0
781-
; RV32IFD-NEXT: seqz a0, a0
782-
; RV32IFD-NEXT: addi s0, a0, -1
773+
; RV32IFD-NEXT: neg s0, a0
783774
; RV32IFD-NEXT: call __fixunsdfdi@plt
784775
; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0)
785776
; RV32IFD-NEXT: fld ft0, %lo(.LCPI14_0)(a2)
786777
; RV32IFD-NEXT: and a0, s0, a0
787778
; RV32IFD-NEXT: flt.d a2, ft0, fs0
788-
; RV32IFD-NEXT: seqz a2, a2
789-
; RV32IFD-NEXT: addi a2, a2, -1
779+
; RV32IFD-NEXT: neg a2, a2
790780
; RV32IFD-NEXT: or a0, a2, a0
791781
; RV32IFD-NEXT: and a1, s0, a1
792782
; RV32IFD-NEXT: or a1, a2, a1
@@ -816,47 +806,45 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
816806
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
817807
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
818808
; RV32I-NEXT: mv s0, a1
819-
; RV32I-NEXT: mv s2, a0
809+
; RV32I-NEXT: mv s1, a0
820810
; RV32I-NEXT: lui a0, 278272
821-
; RV32I-NEXT: addi s3, a0, -1
811+
; RV32I-NEXT: addi s2, a0, -1
822812
; RV32I-NEXT: li a2, -1
823-
; RV32I-NEXT: mv a0, s2
824-
; RV32I-NEXT: mv a3, s3
813+
; RV32I-NEXT: mv a0, s1
814+
; RV32I-NEXT: mv a3, s2
825815
; RV32I-NEXT: call __gtdf2@plt
826816
; RV32I-NEXT: sgtz a0, a0
827-
; RV32I-NEXT: neg s1, a0
828-
; RV32I-NEXT: mv a0, s2
829-
; RV32I-NEXT: mv a1, s0
830-
; RV32I-NEXT: call __fixunsdfdi@plt
831-
; RV32I-NEXT: mv s5, a0
832-
; RV32I-NEXT: mv s4, a1
833-
; RV32I-NEXT: mv a0, s2
817+
; RV32I-NEXT: neg s4, a0
818+
; RV32I-NEXT: mv a0, s1
834819
; RV32I-NEXT: mv a1, s0
835820
; RV32I-NEXT: li a2, 0
836821
; RV32I-NEXT: li a3, 0
837822
; RV32I-NEXT: call __gedf2@plt
838-
; RV32I-NEXT: bltz a0, .LBB14_2
839-
; RV32I-NEXT: # %bb.1: # %start
840-
; RV32I-NEXT: or s1, s1, s5
841-
; RV32I-NEXT: .LBB14_2: # %start
823+
; RV32I-NEXT: slti a0, a0, 0
824+
; RV32I-NEXT: addi s5, a0, -1
825+
; RV32I-NEXT: mv a0, s1
826+
; RV32I-NEXT: mv a1, s0
827+
; RV32I-NEXT: call __fixunsdfdi@plt
828+
; RV32I-NEXT: mv s3, a1
829+
; RV32I-NEXT: and a0, s5, a0
830+
; RV32I-NEXT: or s4, s4, a0
842831
; RV32I-NEXT: li a2, -1
843-
; RV32I-NEXT: mv a0, s2
832+
; RV32I-NEXT: mv a0, s1
844833
; RV32I-NEXT: mv a1, s0
845-
; RV32I-NEXT: mv a3, s3
834+
; RV32I-NEXT: mv a3, s2
846835
; RV32I-NEXT: call __gtdf2@plt
847836
; RV32I-NEXT: sgtz a0, a0
848-
; RV32I-NEXT: neg s3, a0
849-
; RV32I-NEXT: mv a0, s2
837+
; RV32I-NEXT: neg s2, a0
838+
; RV32I-NEXT: mv a0, s1
850839
; RV32I-NEXT: mv a1, s0
851840
; RV32I-NEXT: li a2, 0
852841
; RV32I-NEXT: li a3, 0
853842
; RV32I-NEXT: call __gedf2@plt
854-
; RV32I-NEXT: bltz a0, .LBB14_4
855-
; RV32I-NEXT: # %bb.3: # %start
856-
; RV32I-NEXT: or s3, s3, s4
857-
; RV32I-NEXT: .LBB14_4: # %start
858-
; RV32I-NEXT: mv a0, s1
859-
; RV32I-NEXT: mv a1, s3
843+
; RV32I-NEXT: slti a0, a0, 0
844+
; RV32I-NEXT: addi a0, a0, -1
845+
; RV32I-NEXT: and a0, a0, s3
846+
; RV32I-NEXT: or a1, s2, a0
847+
; RV32I-NEXT: mv a0, s4
860848
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
861849
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
862850
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
@@ -873,30 +861,25 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
873861
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
874862
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
875863
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
876-
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
877-
; RV64I-NEXT: mv s2, a0
864+
; RV64I-NEXT: mv s0, a0
865+
; RV64I-NEXT: li a1, 0
866+
; RV64I-NEXT: call __gedf2@plt
867+
; RV64I-NEXT: slti a0, a0, 0
868+
; RV64I-NEXT: addi s1, a0, -1
869+
; RV64I-NEXT: mv a0, s0
870+
; RV64I-NEXT: call __fixunsdfdi@plt
871+
; RV64I-NEXT: and s1, s1, a0
878872
; RV64I-NEXT: li a0, 1087
879873
; RV64I-NEXT: slli a0, a0, 52
880874
; RV64I-NEXT: addi a1, a0, -1
881-
; RV64I-NEXT: mv a0, s2
875+
; RV64I-NEXT: mv a0, s0
882876
; RV64I-NEXT: call __gtdf2@plt
883877
; RV64I-NEXT: sgtz a0, a0
884-
; RV64I-NEXT: neg s0, a0
885-
; RV64I-NEXT: mv a0, s2
886-
; RV64I-NEXT: call __fixunsdfdi@plt
887-
; RV64I-NEXT: mv s1, a0
888-
; RV64I-NEXT: mv a0, s2
889-
; RV64I-NEXT: li a1, 0
890-
; RV64I-NEXT: call __gedf2@plt
891-
; RV64I-NEXT: bltz a0, .LBB14_2
892-
; RV64I-NEXT: # %bb.1: # %start
893-
; RV64I-NEXT: or s0, s0, s1
894-
; RV64I-NEXT: .LBB14_2: # %start
895-
; RV64I-NEXT: mv a0, s0
878+
; RV64I-NEXT: neg a0, a0
879+
; RV64I-NEXT: or a0, a0, s1
896880
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
897881
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
898882
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
899-
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
900883
; RV64I-NEXT: addi sp, sp, 32
901884
; RV64I-NEXT: ret
902885
start:
@@ -1916,29 +1899,27 @@ define zeroext i32 @fcvt_wu_d_sat_zext(double %a) nounwind {
19161899
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
19171900
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
19181901
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
1919-
; RV32I-NEXT: mv s2, a1
1920-
; RV32I-NEXT: mv s3, a0
1902+
; RV32I-NEXT: mv s0, a1
1903+
; RV32I-NEXT: mv s1, a0
19211904
; RV32I-NEXT: lui a0, 270080
19221905
; RV32I-NEXT: addi a3, a0, -1
19231906
; RV32I-NEXT: lui a2, 1048064
1924-
; RV32I-NEXT: mv a0, s3
1907+
; RV32I-NEXT: mv a0, s1
19251908
; RV32I-NEXT: call __gtdf2@plt
19261909
; RV32I-NEXT: sgtz a0, a0
1927-
; RV32I-NEXT: neg s0, a0
1928-
; RV32I-NEXT: mv a0, s3
1929-
; RV32I-NEXT: mv a1, s2
1930-
; RV32I-NEXT: call __fixunsdfsi@plt
1931-
; RV32I-NEXT: mv s1, a0
1932-
; RV32I-NEXT: mv a0, s3
1933-
; RV32I-NEXT: mv a1, s2
1910+
; RV32I-NEXT: neg s2, a0
1911+
; RV32I-NEXT: mv a0, s1
1912+
; RV32I-NEXT: mv a1, s0
19341913
; RV32I-NEXT: li a2, 0
19351914
; RV32I-NEXT: li a3, 0
19361915
; RV32I-NEXT: call __gedf2@plt
1937-
; RV32I-NEXT: bltz a0, .LBB33_2
1938-
; RV32I-NEXT: # %bb.1: # %start
1939-
; RV32I-NEXT: or s0, s0, s1
1940-
; RV32I-NEXT: .LBB33_2: # %start
1941-
; RV32I-NEXT: mv a0, s0
1916+
; RV32I-NEXT: slti a0, a0, 0
1917+
; RV32I-NEXT: addi s3, a0, -1
1918+
; RV32I-NEXT: mv a0, s1
1919+
; RV32I-NEXT: mv a1, s0
1920+
; RV32I-NEXT: call __fixunsdfsi@plt
1921+
; RV32I-NEXT: and a0, s3, a0
1922+
; RV32I-NEXT: or a0, s2, a0
19421923
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
19431924
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
19441925
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload

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