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ellishgellishg
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[regalloc][basic] Change spill weight for optsize funcs (#112960)
Change the spill weight calculations for `optsize` functions to remove the block frequency multiplier. For those functions, we do not want to consider the runtime cost of spilling, only the codesize cost. I built a large app with the basic and greedy (default) register allocator enabled. | Regalloc Type | Uncompressed Size Delta | Compressed Size Delta | | - | - | - | | Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) | | Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) | Since I only saw a size win with the basic register allocator, I decided to only change the behavior for that type.
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6 files changed

+205
-12
lines changed

‎llvm/include/llvm/CodeGen/CalcSpillWeights.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ class LiveIntervals;
1818
class MachineBlockFrequencyInfo;
1919
class MachineFunction;
2020
class MachineLoopInfo;
21+
class ProfileSummaryInfo;
2122
class VirtRegMap;
2223

2324
/// Normalize the spill weight of a live interval
@@ -47,6 +48,7 @@ class VirtRegMap;
4748
LiveIntervals &LIS;
4849
const VirtRegMap &VRM;
4950
const MachineLoopInfo &Loops;
51+
ProfileSummaryInfo *PSI;
5052
const MachineBlockFrequencyInfo &MBFI;
5153

5254
/// Returns true if Reg of live interval LI is used in instruction with many
@@ -56,8 +58,9 @@ class VirtRegMap;
5658
public:
5759
VirtRegAuxInfo(MachineFunction &MF, LiveIntervals &LIS,
5860
const VirtRegMap &VRM, const MachineLoopInfo &Loops,
59-
const MachineBlockFrequencyInfo &MBFI)
60-
: MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), MBFI(MBFI) {}
61+
const MachineBlockFrequencyInfo &MBFI,
62+
ProfileSummaryInfo *PSI = nullptr)
63+
: MF(MF), LIS(LIS), VRM(VRM), Loops(Loops), PSI(PSI), MBFI(MBFI) {}
6164

6265
virtual ~VirtRegAuxInfo() = default;
6366

‎llvm/include/llvm/CodeGen/LiveIntervals.h

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ class MachineDominatorTree;
4747
class MachineFunction;
4848
class MachineInstr;
4949
class MachineRegisterInfo;
50+
class ProfileSummaryInfo;
5051
class raw_ostream;
5152
class TargetInstrInfo;
5253
class VirtRegMap;
@@ -113,14 +114,18 @@ class LiveIntervals {
113114
~LiveIntervals();
114115

115116
/// Calculate the spill weight to assign to a single instruction.
117+
/// If \p PSI is provided the calculation is altered for optsize functions.
116118
static float getSpillWeight(bool isDef, bool isUse,
117119
const MachineBlockFrequencyInfo *MBFI,
118-
const MachineInstr &MI);
120+
const MachineInstr &MI,
121+
ProfileSummaryInfo *PSI = nullptr);
119122

120123
/// Calculate the spill weight to assign to a single instruction.
124+
/// If \p PSI is provided the calculation is altered for optsize functions.
121125
static float getSpillWeight(bool isDef, bool isUse,
122126
const MachineBlockFrequencyInfo *MBFI,
123-
const MachineBasicBlock *MBB);
127+
const MachineBasicBlock *MBB,
128+
ProfileSummaryInfo *PSI = nullptr);
124129

125130
LiveInterval &getInterval(Register Reg) {
126131
if (hasInterval(Reg))

‎llvm/lib/CodeGen/CalcSpillWeights.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -199,8 +199,10 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
199199
// localLI = COPY other
200200
// ...
201201
// other = COPY localLI
202-
TotalWeight += LiveIntervals::getSpillWeight(true, false, &MBFI, LocalMBB);
203-
TotalWeight += LiveIntervals::getSpillWeight(false, true, &MBFI, LocalMBB);
202+
TotalWeight +=
203+
LiveIntervals::getSpillWeight(true, false, &MBFI, LocalMBB, PSI);
204+
TotalWeight +=
205+
LiveIntervals::getSpillWeight(false, true, &MBFI, LocalMBB, PSI);
204206

205207
NumInstr += 2;
206208
}
@@ -272,7 +274,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
272274
// Calculate instr weight.
273275
bool Reads, Writes;
274276
std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg());
275-
Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI);
277+
Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI, PSI);
276278

277279
// Give extra weight to what looks like a loop induction variable update.
278280
if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB))

‎llvm/lib/CodeGen/LiveIntervals.cpp

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,13 +30,15 @@
3030
#include "llvm/CodeGen/MachineInstrBundle.h"
3131
#include "llvm/CodeGen/MachineOperand.h"
3232
#include "llvm/CodeGen/MachineRegisterInfo.h"
33+
#include "llvm/CodeGen/MachineSizeOpts.h"
3334
#include "llvm/CodeGen/Passes.h"
3435
#include "llvm/CodeGen/SlotIndexes.h"
3536
#include "llvm/CodeGen/StackMaps.h"
3637
#include "llvm/CodeGen/TargetRegisterInfo.h"
3738
#include "llvm/CodeGen/TargetSubtargetInfo.h"
3839
#include "llvm/CodeGen/VirtRegMap.h"
3940
#include "llvm/Config/llvm-config.h"
41+
#include "llvm/IR/ProfileSummary.h"
4042
#include "llvm/IR/Statepoint.h"
4143
#include "llvm/MC/LaneBitmask.h"
4244
#include "llvm/MC/MCRegisterInfo.h"
@@ -875,14 +877,23 @@ LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
875877

876878
float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
877879
const MachineBlockFrequencyInfo *MBFI,
878-
const MachineInstr &MI) {
879-
return getSpillWeight(isDef, isUse, MBFI, MI.getParent());
880+
const MachineInstr &MI,
881+
ProfileSummaryInfo *PSI) {
882+
return getSpillWeight(isDef, isUse, MBFI, MI.getParent(), PSI);
880883
}
881884

882885
float LiveIntervals::getSpillWeight(bool isDef, bool isUse,
883886
const MachineBlockFrequencyInfo *MBFI,
884-
const MachineBasicBlock *MBB) {
885-
return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB);
887+
const MachineBasicBlock *MBB,
888+
ProfileSummaryInfo *PSI) {
889+
float Weight = isDef + isUse;
890+
const auto *MF = MBB->getParent();
891+
// When optimizing for size we only consider the codesize impact of spilling
892+
// the register, not the runtime impact.
893+
if (PSI && (MF->getFunction().hasOptSize() ||
894+
llvm::shouldOptimizeForSize(MF, PSI, MBFI)))
895+
return Weight;
896+
return Weight * MBFI->getBlockFreqRelativeToEntryBlock(MBB);
886897
}
887898

888899
LiveRange::Segment

‎llvm/lib/CodeGen/RegAllocBasic.cpp

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "AllocationOrder.h"
1515
#include "RegAllocBase.h"
1616
#include "llvm/Analysis/AliasAnalysis.h"
17+
#include "llvm/Analysis/ProfileSummaryInfo.h"
1718
#include "llvm/CodeGen/CalcSpillWeights.h"
1819
#include "llvm/CodeGen/LiveDebugVariables.h"
1920
#include "llvm/CodeGen/LiveIntervals.h"
@@ -140,6 +141,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
140141
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
141142
INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
142143
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
144+
INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
143145
INITIALIZE_PASS_END(RABasic, "regallocbasic", "Basic Register Allocator", false,
144146
false)
145147

@@ -182,6 +184,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
182184
AU.addPreserved<LiveDebugVariables>();
183185
AU.addRequired<LiveStacks>();
184186
AU.addPreserved<LiveStacks>();
187+
AU.addRequired<ProfileSummaryInfoWrapperPass>();
185188
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
186189
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
187190
AU.addRequiredID(MachineDominatorsID);
@@ -312,7 +315,8 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
312315
getAnalysis<LiveRegMatrix>());
313316
VirtRegAuxInfo VRAI(
314317
*MF, *LIS, *VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
315-
getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI());
318+
getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(),
319+
&getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
316320
VRAI.calculateSpillWeightsAndHints();
317321

318322
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM, VRAI));

‎llvm/test/CodeGen/AArch64/regalloc-spill-weight-basic.ll

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,168 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
3+
; RUN: llc < %s -mtriple=aarch64 -regalloc=basic | FileCheck %s
4+
5+
; Test that the register allocator behaves differently with minsize functions.
6+
7+
declare void @foo(i32, ptr)
8+
9+
define void @optsize(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) minsize {
10+
; CHECK-LABEL: optsize:
11+
; CHECK: // %bb.0: // %bb
12+
; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
13+
; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
14+
; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
15+
; CHECK-NEXT: .cfi_def_cfa_offset 48
16+
; CHECK-NEXT: .cfi_offset w19, -8
17+
; CHECK-NEXT: .cfi_offset w20, -16
18+
; CHECK-NEXT: .cfi_offset w21, -24
19+
; CHECK-NEXT: .cfi_offset w22, -32
20+
; CHECK-NEXT: .cfi_offset w23, -40
21+
; CHECK-NEXT: .cfi_offset w30, -48
22+
; CHECK-NEXT: mov w23, w5
23+
; CHECK-NEXT: mov x22, x4
24+
; CHECK-NEXT: mov x21, x3
25+
; CHECK-NEXT: mov x20, x2
26+
; CHECK-NEXT: mov w19, w1
27+
; CHECK-NEXT: .LBB0_1: // %bb8
28+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
29+
; CHECK-NEXT: cbz w19, .LBB0_1
30+
; CHECK-NEXT: // %bb.2: // %bb8
31+
; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
32+
; CHECK-NEXT: cmp w19, #39
33+
; CHECK-NEXT: b.eq .LBB0_6
34+
; CHECK-NEXT: // %bb.3: // %bb8
35+
; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
36+
; CHECK-NEXT: cmp w19, #34
37+
; CHECK-NEXT: b.eq .LBB0_6
38+
; CHECK-NEXT: // %bb.4: // %bb8
39+
; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
40+
; CHECK-NEXT: cmp w19, #10
41+
; CHECK-NEXT: b.ne .LBB0_1
42+
; CHECK-NEXT: // %bb.5: // %bb9
43+
; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
44+
; CHECK-NEXT: str wzr, [x20]
45+
; CHECK-NEXT: b .LBB0_1
46+
; CHECK-NEXT: .LBB0_6: // %bb10
47+
; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
48+
; CHECK-NEXT: mov w0, w23
49+
; CHECK-NEXT: mov x1, x21
50+
; CHECK-NEXT: str wzr, [x22]
51+
; CHECK-NEXT: bl foo
52+
; CHECK-NEXT: b .LBB0_1
53+
bb:
54+
br label %bb7
55+
56+
bb7: ; preds = %bb13, %bb
57+
%phi = phi i32 [ 0, %bb ], [ %spec.select, %bb13 ]
58+
br label %bb8
59+
60+
bb8: ; preds = %bb10, %bb9, %bb8, %bb7
61+
switch i32 %arg1, label %bb8 [
62+
i32 10, label %bb9
63+
i32 1, label %bb16
64+
i32 0, label %bb13
65+
i32 39, label %bb10
66+
i32 34, label %bb10
67+
]
68+
69+
bb9: ; preds = %bb8
70+
store i32 0, ptr %arg2, align 4
71+
br label %bb8
72+
73+
bb10: ; preds = %bb8, %bb8
74+
store i32 0, ptr %arg4, align 4
75+
tail call void @foo(i32 %arg5, ptr %arg3)
76+
br label %bb8
77+
78+
bb13: ; preds = %bb8
79+
%not.arg6 = xor i1 %arg6, true
80+
%spec.select = zext i1 %not.arg6 to i32
81+
br label %bb7
82+
83+
bb16: ; preds = %bb8
84+
unreachable
85+
}
86+
87+
define void @optspeed(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) {
88+
; CHECK-LABEL: optspeed:
89+
; CHECK: // %bb.0: // %bb
90+
; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
91+
; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
92+
; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
93+
; CHECK-NEXT: .cfi_def_cfa_offset 48
94+
; CHECK-NEXT: .cfi_offset w19, -8
95+
; CHECK-NEXT: .cfi_offset w20, -16
96+
; CHECK-NEXT: .cfi_offset w21, -24
97+
; CHECK-NEXT: .cfi_offset w22, -32
98+
; CHECK-NEXT: .cfi_offset w23, -40
99+
; CHECK-NEXT: .cfi_offset w30, -48
100+
; CHECK-NEXT: mov w22, w5
101+
; CHECK-NEXT: mov x21, x4
102+
; CHECK-NEXT: mov x20, x3
103+
; CHECK-NEXT: mov x23, x2
104+
; CHECK-NEXT: mov w19, w1
105+
; CHECK-NEXT: b .LBB1_2
106+
; CHECK-NEXT: .LBB1_1: // %bb10
107+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
108+
; CHECK-NEXT: mov w0, w22
109+
; CHECK-NEXT: mov x1, x20
110+
; CHECK-NEXT: str wzr, [x21]
111+
; CHECK-NEXT: bl foo
112+
; CHECK-NEXT: .LBB1_2: // %bb8
113+
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
114+
; CHECK-NEXT: cmp w19, #33
115+
; CHECK-NEXT: b.gt .LBB1_6
116+
; CHECK-NEXT: // %bb.3: // %bb8
117+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
118+
; CHECK-NEXT: cbz w19, .LBB1_2
119+
; CHECK-NEXT: // %bb.4: // %bb8
120+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
121+
; CHECK-NEXT: cmp w19, #10
122+
; CHECK-NEXT: b.ne .LBB1_2
123+
; CHECK-NEXT: // %bb.5: // %bb9
124+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
125+
; CHECK-NEXT: str wzr, [x23]
126+
; CHECK-NEXT: b .LBB1_2
127+
; CHECK-NEXT: .LBB1_6: // %bb8
128+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
129+
; CHECK-NEXT: cmp w19, #34
130+
; CHECK-NEXT: b.eq .LBB1_1
131+
; CHECK-NEXT: // %bb.7: // %bb8
132+
; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
133+
; CHECK-NEXT: cmp w19, #39
134+
; CHECK-NEXT: b.eq .LBB1_1
135+
; CHECK-NEXT: b .LBB1_2
136+
bb:
137+
br label %bb7
138+
139+
bb7: ; preds = %bb13, %bb
140+
%phi = phi i32 [ 0, %bb ], [ %spec.select, %bb13 ]
141+
br label %bb8
142+
143+
bb8: ; preds = %bb10, %bb9, %bb8, %bb7
144+
switch i32 %arg1, label %bb8 [
145+
i32 10, label %bb9
146+
i32 1, label %bb16
147+
i32 0, label %bb13
148+
i32 39, label %bb10
149+
i32 34, label %bb10
150+
]
151+
152+
bb9: ; preds = %bb8
153+
store i32 0, ptr %arg2, align 4
154+
br label %bb8
155+
156+
bb10: ; preds = %bb8, %bb8
157+
store i32 0, ptr %arg4, align 4
158+
tail call void @foo(i32 %arg5, ptr %arg3)
159+
br label %bb8
160+
161+
bb13: ; preds = %bb8
162+
%not.arg6 = xor i1 %arg6, true
163+
%spec.select = zext i1 %not.arg6 to i32
164+
br label %bb7
165+
166+
bb16: ; preds = %bb8
167+
unreachable
168+
}

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