Skip to content

Commit e7086d6

Browse files
michaelmaitlandmichaelmaitland
committed
fixup! respond to review comments
1 parent 4771bee commit e7086d6

File tree

3 files changed

+58
-18
lines changed

3 files changed

+58
-18
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1034,7 +1034,7 @@ bool RISCVLegalizerInfo::legalizeExtractSubvector(MachineInstr &MI,
10341034
assert(SubRegIdx != RISCV::NoSubRegister);
10351035
InterLitTy = getLMUL1Ty(BigTy);
10361036
// SDAG builds a TargetExtractSubreg. A Copy with SubReg specified on the
1037-
// source Register is the equivalent.
1037+
// source Register is the equivalent.
10381038
Vec = MIB.buildInstr(TargetOpcode::COPY, {InterLitTy}, {})
10391039
.addReg(Vec, 0, SubRegIdx)
10401040
.getReg(0);

‎llvm/lib/Target/RISCV/RISCVInstrGISel.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ def G_SPLAT_VECTOR_SPLIT_I64_VL : RISCVGenericInstruction {
6262
def G_VSLIDEDOWN_VL : RISCVGenericInstruction {
6363
let OutOperandList = (outs type0:$dst);
6464
let InOperandList = (ins type0:$merge, type0:$vec, type1:$idx, type2:$mask,
65-
type3:$vl, type4:$policy);
65+
type1:$vl, type1:$policy);
6666
let hasSideEffects = false;
6767
}
6868
def : GINodeEquiv<G_VSLIDEDOWN_VL, riscv_slidedown_vl>;

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-extract-subvector.mir

Lines changed: 56 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -278,13 +278,33 @@ legalized: false
278278
tracksRegLiveness: true
279279
body: |
280280
bb.0.entry:
281-
; CHECK-LABEL: name: extract_subvector_nxv2i8
282-
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
283-
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s8>), 0
284-
; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)
285-
; CHECK-NEXT: PseudoRET implicit $v8
281+
; RV32-LABEL: name: extract_subvector_nxv2i8
282+
; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
283+
; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
284+
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
285+
; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
286+
; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
287+
; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
288+
; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), $x0, 3
289+
; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s8>), 0
290+
; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 1 x s8>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)
291+
; RV32-NEXT: $v8 = COPY [[BITCAST]](<vscale x 1 x s8>)
292+
; RV32-NEXT: PseudoRET implicit $v8
293+
;
294+
; RV64-LABEL: name: extract_subvector_nxv2i8
295+
; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
296+
; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
297+
; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
298+
; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
299+
; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
300+
; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
301+
; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), $x0, 3
302+
; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s8>), 0
303+
; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 1 x s8>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)
304+
; RV64-NEXT: $v8 = COPY [[BITCAST]](<vscale x 1 x s8>)
305+
; RV64-NEXT: PseudoRET implicit $v8
286306
%0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF
287-
%1:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR %0(<vscale x 2 x s8>), 0
307+
%1:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR %0(<vscale x 2 x s8>), 1
288308
$v8 = COPY %1(<vscale x 1 x s8>)
289309
PseudoRET implicit $v8
290310
...
@@ -294,13 +314,33 @@ legalized: false
294314
tracksRegLiveness: true
295315
body: |
296316
bb.0.entry:
297-
; CHECK-LABEL: name: extract_subvector_nxv4i16
298-
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
299-
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s16>), 0
300-
; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s16>)
301-
; CHECK-NEXT: PseudoRET implicit $v8
317+
; RV32-LABEL: name: extract_subvector_nxv4i16
318+
; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
319+
; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB
320+
; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
321+
; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)
322+
; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
323+
; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
324+
; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEDOWN_VL [[DEF1]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), $x0, 3
325+
; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s16>), 0
326+
; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 1 x s16>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 1 x s16>)
327+
; RV32-NEXT: $v8 = COPY [[BITCAST]](<vscale x 1 x s16>)
328+
; RV32-NEXT: PseudoRET implicit $v8
329+
;
330+
; RV64-LABEL: name: extract_subvector_nxv4i16
331+
; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
332+
; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB
333+
; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
334+
; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)
335+
; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL $x0
336+
; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
337+
; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEDOWN_VL [[DEF1]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), $x0, 3
338+
; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s16>), 0
339+
; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 1 x s16>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 1 x s16>)
340+
; RV64-NEXT: $v8 = COPY [[BITCAST]](<vscale x 1 x s16>)
341+
; RV64-NEXT: PseudoRET implicit $v8
302342
%0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF
303-
%1:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s16>), 0
343+
%1:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s16>), 2
304344
$v8 = COPY %1(<vscale x 1 x s16>)
305345
PseudoRET implicit $v8
306346
...
@@ -312,11 +352,11 @@ body: |
312352
bb.0.entry:
313353
; CHECK-LABEL: name: extract_subvector_nxv8i32
314354
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
315-
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0
355+
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 4
316356
; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>)
317357
; CHECK-NEXT: PseudoRET implicit $v8
318358
%0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF
319-
%1:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s32>), 0
359+
%1:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s32>), 4
320360
$v8 = COPY %1(<vscale x 4 x s32>)
321361
PseudoRET implicit $v8
322362
...
@@ -328,11 +368,11 @@ body: |
328368
bb.0.entry:
329369
; CHECK-LABEL: name: extract_subvector_nxv8i64
330370
; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
331-
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0
371+
; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 2
332372
; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 2 x s64>)
333373
; CHECK-NEXT: PseudoRET implicit $v8
334374
%0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF
335-
%1:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s64>), 0
375+
%1:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s64>), 2
336376
$v8 = COPY %1(<vscale x 2 x s64>)
337377
PseudoRET implicit $v8
338378
...

0 commit comments

Comments
 (0)