change variable names

Author: mihajlovicana

llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp

@@ -16,12 +16,7 @@
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
 #include "SIInstrInfo.h"
-#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/MC/MCRegister.h"
-#include "llvm/Support/ErrorHandling.h"
-
 using namespace llvm;
 
 #define DEBUG_TYPE "amdgpu-insert-delay-alu"
@@ -56,10 +51,7 @@ class AMDGPUInsertDelayAlu {
     // These instruction types wait for VA_SDST==0 before issuing.
     const uint64_t VA_SDST_0 = SIInstrFlags::SALU | SIInstrFlags::SMRD;
 
-    if (MI.getDesc().TSFlags & VA_SDST_0)
-      return true;
-
-    return false;
+    return MI.getDesc().TSFlags & VA_SDST_0;
   }
 
   // Types of delay that can be encoded in an s_delay_alu instruction.
@@ -242,12 +234,11 @@ class AMDGPUInsertDelayAlu {
       }
     }
 
-    void advanceByNum(DelayType Type, unsigned Cycles,
-                      unsigned SGPRWriteVALUNum) {
+    void advanceByVALUNum(unsigned VALUNum) {
       iterator Next;
       for (auto I = begin(), E = end(); I != E; I = Next) {
         Next = std::next(I);
-        if (I->second.VALUNum >= SGPRWriteVALUNum && I->second.VALUCycles > 0) {
+        if (I->second.VALUNum >= VALUNum && I->second.VALUCycles > 0) {
           erase(I);
         }
       }
@@ -357,7 +348,7 @@ class AMDGPUInsertDelayAlu {
     bool Changed = false;
     MachineInstr *LastDelayAlu = nullptr;
 
-    MCRegUnit lastSGPRfromVALU = 0;
+    MCRegUnit LastSGPRFromVALU = 0;
     // Iterate over the contents of bundles, but don't emit any instructions
     // inside a bundle.
     for (auto &MI : MBB.instrs()) {
@@ -373,11 +364,11 @@ class AMDGPUInsertDelayAlu {
       DelayType Type = getDelayType(MI.getDesc().TSFlags);
 
       if (instructionWaitsForSGPRWrites(MI)) {
-        auto It = State.find(lastSGPRfromVALU);
+        auto It = State.find(LastSGPRFromVALU);
         if (It != State.end()) {
           DelayInfo Info = It->getSecond();
-          State.advanceByNum(VALU, Info.VALUCycles, Info.VALUNum);
-          lastSGPRfromVALU = 0;
+          State.advanceByVALUNum(Info.VALUNum);
+          LastSGPRFromVALU = 0;
         }
       }
 
@@ -409,7 +400,7 @@ class AMDGPUInsertDelayAlu {
           for (const auto &Op : MI.defs()) {
             Register Reg = Op.getReg();
             if (AMDGPU::isSGPR(Reg, TRI)) {
-              lastSGPRfromVALU = *(TRI->regunits(Reg).begin());
+              LastSGPRFromVALU = *TRI->regunits(Reg).begin();
               break;
             }
           }

llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-memcpy.ll

@@ -923,7 +923,6 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) inreg %src, ptr
 ; SDAG-GFX1100-NEXT:    v_add_nc_u32_e32 v61, s0, v0
 ; SDAG-GFX1100-NEXT:    v_add_nc_u32_e32 v65, s8, v0
 ; SDAG-GFX1100-NEXT:    v_add_co_u32 v0, s1, 0x100, v0
-; SDAG-GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; SDAG-GFX1100-NEXT:    s_and_b32 vcc_lo, exec_lo, s1
 ; SDAG-GFX1100-NEXT:    s_clause 0xf
 ; SDAG-GFX1100-NEXT:    buffer_load_b128 v[1:4], v61, s[4:7], 0 offen
@@ -1097,7 +1096,6 @@ define amdgpu_kernel void @memcpy_known_medium(ptr addrspace(7) inreg %src, ptr
 ; GISEL-GFX1100-NEXT:    v_add_nc_u32_e32 v61, s0, v0
 ; GISEL-GFX1100-NEXT:    v_add_nc_u32_e32 v65, s8, v0
 ; GISEL-GFX1100-NEXT:    v_add_co_u32 v0, s1, 0x100, v0
-; GISEL-GFX1100-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GISEL-GFX1100-NEXT:    s_xor_b32 s1, s1, -1
 ; GISEL-GFX1100-NEXT:    s_clause 0xf
 ; GISEL-GFX1100-NEXT:    buffer_load_b128 v[1:4], v61, s[4:7], 0 offen

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.m0.ll

@@ -22,7 +22,6 @@ define void @test_readfirstlane_m0(i32 %arg) {
 ; GFX11:       ; %bb.0:
 ; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-NEXT:    s_mov_b32 m0, s0
 ; GFX11-NEXT:    s_sendmsg sendmsg(MSG_INTERRUPT)
 ; GFX11-NEXT:    s_waitcnt lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.ttracedata.ll

@@ -26,18 +26,12 @@ define amdgpu_cs void @ttracedata_s(i32 inreg %val) {
 }
 
 define amdgpu_cs void @ttracedata_v(i32 %val) {
-; GFX11-SDAG-LABEL: ttracedata_v:
-; GFX11-SDAG:       ; %bb.0:
-; GFX11-SDAG-NEXT:    v_readfirstlane_b32 s0, v0
-; GFX11-SDAG-NEXT:    s_mov_b32 m0, s0
-; GFX11-SDAG-NEXT:    s_ttracedata
-; GFX11-SDAG-NEXT:    s_endpgm
-;
-; GFX11-GISEL-LABEL: ttracedata_v:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    v_readfirstlane_b32 m0, v0
-; GFX11-GISEL-NEXT:    s_ttracedata
-; GFX11-GISEL-NEXT:    s_endpgm
+; GFX11-LABEL: ttracedata_v:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    s_mov_b32 m0, s0
+; GFX11-NEXT:    s_ttracedata
+; GFX11-NEXT:    s_endpgm
   call void @llvm.amdgcn.s.ttracedata(i32 %val)
   ret void
 }