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sgundapasgundapa
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Scalarize the vector inputs to llvm.lround intrinsic by default. (#101054)
Verifier is updated in a different patch to let the vector types for llvm.lround and llvm.llround intrinsics.
1 parent c61d565 commit e78156a

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9 files changed

+424
-96
lines changed

9 files changed

+424
-96
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4921,6 +4921,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
49214921
case G_INTRINSIC_LLRINT:
49224922
case G_INTRINSIC_ROUND:
49234923
case G_INTRINSIC_ROUNDEVEN:
4924+
case G_LROUND:
4925+
case G_LLROUND:
49244926
case G_INTRINSIC_TRUNC:
49254927
case G_FCOS:
49264928
case G_FSIN:

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -507,7 +507,7 @@ namespace {
507507
SDValue visitUINT_TO_FP(SDNode *N);
508508
SDValue visitFP_TO_SINT(SDNode *N);
509509
SDValue visitFP_TO_UINT(SDNode *N);
510-
SDValue visitXRINT(SDNode *N);
510+
SDValue visitXROUND(SDNode *N);
511511
SDValue visitFP_ROUND(SDNode *N);
512512
SDValue visitFP_EXTEND(SDNode *N);
513513
SDValue visitFNEG(SDNode *N);
@@ -1929,8 +1929,10 @@ SDValue DAGCombiner::visit(SDNode *N) {
19291929
case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
19301930
case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
19311931
case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1932+
case ISD::LROUND:
1933+
case ISD::LLROUND:
19321934
case ISD::LRINT:
1933-
case ISD::LLRINT: return visitXRINT(N);
1935+
case ISD::LLRINT: return visitXROUND(N);
19341936
case ISD::FP_ROUND: return visitFP_ROUND(N);
19351937
case ISD::FP_EXTEND: return visitFP_EXTEND(N);
19361938
case ISD::FNEG: return visitFNEG(N);
@@ -17998,15 +18000,17 @@ SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1799818000
return FoldIntToFPToInt(N, DAG);
1799918001
}
1800018002

18001-
SDValue DAGCombiner::visitXRINT(SDNode *N) {
18003+
SDValue DAGCombiner::visitXROUND(SDNode *N) {
1800218004
SDValue N0 = N->getOperand(0);
1800318005
EVT VT = N->getValueType(0);
1800418006

1800518007
// fold (lrint|llrint undef) -> undef
18008+
// fold (lround|llround undef) -> undef
1800618009
if (N0.isUndef())
1800718010
return DAG.getUNDEF(VT);
1800818011

1800918012
// fold (lrint|llrint c1fp) -> c1
18013+
// fold (lround|llround c1fp) -> c1
1801018014
if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
1801118015
return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0);
1801218016

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2441,6 +2441,8 @@ bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
24412441
case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
24422442
case ISD::FP_TO_SINT:
24432443
case ISD::FP_TO_UINT:
2444+
case ISD::LROUND:
2445+
case ISD::LLROUND:
24442446
case ISD::LRINT:
24452447
case ISD::LLRINT: R = PromoteFloatOp_UnaryOp(N, OpNo); break;
24462448
case ISD::FP_TO_SINT_SAT:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1052,7 +1052,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
10521052
SDValue WidenVecRes_Convert(SDNode *N);
10531053
SDValue WidenVecRes_Convert_StrictFP(SDNode *N);
10541054
SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N);
1055-
SDValue WidenVecRes_XRINT(SDNode *N);
1055+
SDValue WidenVecRes_XROUND(SDNode *N);
10561056
SDValue WidenVecRes_FCOPYSIGN(SDNode *N);
10571057
SDValue WidenVecRes_UnarySameEltsWithScalarArg(SDNode *N);
10581058
SDValue WidenVecRes_ExpOp(SDNode *N);

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
473473
Node->getValueType(0), Scale);
474474
break;
475475
}
476+
case ISD::LROUND:
477+
case ISD::LLROUND:
476478
case ISD::LRINT:
477479
case ISD::LLRINT:
478480
case ISD::SINT_TO_FP:

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
110110
case ISD::LLRINT:
111111
case ISD::FROUND:
112112
case ISD::FROUNDEVEN:
113+
case ISD::LROUND:
114+
case ISD::LLROUND:
113115
case ISD::FSIN:
114116
case ISD::FSINH:
115117
case ISD::FSQRT:
@@ -752,6 +754,8 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
752754
case ISD::FP_TO_UINT:
753755
case ISD::SINT_TO_FP:
754756
case ISD::UINT_TO_FP:
757+
case ISD::LROUND:
758+
case ISD::LLROUND:
755759
case ISD::LRINT:
756760
case ISD::LLRINT:
757761
Res = ScalarizeVecOp_UnaryOp(N);
@@ -1215,6 +1219,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
12151219
case ISD::VP_FROUND:
12161220
case ISD::FROUNDEVEN:
12171221
case ISD::VP_FROUNDEVEN:
1222+
case ISD::LROUND:
1223+
case ISD::LLROUND:
12181224
case ISD::FSIN:
12191225
case ISD::FSINH:
12201226
case ISD::FSQRT: case ISD::VP_SQRT:
@@ -3270,6 +3276,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
32703276
case ISD::ZERO_EXTEND:
32713277
case ISD::ANY_EXTEND:
32723278
case ISD::FTRUNC:
3279+
case ISD::LROUND:
3280+
case ISD::LLROUND:
32733281
case ISD::LRINT:
32743282
case ISD::LLRINT:
32753283
Res = SplitVecOp_UnaryOp(N);
@@ -4594,7 +4602,9 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
45944602
case ISD::LLRINT:
45954603
case ISD::VP_LRINT:
45964604
case ISD::VP_LLRINT:
4597-
Res = WidenVecRes_XRINT(N);
4605+
case ISD::LROUND:
4606+
case ISD::LLROUND:
4607+
Res = WidenVecRes_XROUND(N);
45984608
break;
45994609

46004610
case ISD::FABS:
@@ -5231,7 +5241,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_FP_TO_XINT_SAT(SDNode *N) {
52315241
return DAG.getNode(N->getOpcode(), dl, WidenVT, Src, N->getOperand(1));
52325242
}
52335243

5234-
SDValue DAGTypeLegalizer::WidenVecRes_XRINT(SDNode *N) {
5244+
SDValue DAGTypeLegalizer::WidenVecRes_XROUND(SDNode *N) {
52355245
SDLoc dl(N);
52365246
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
52375247
ElementCount WidenNumElts = WidenVT.getVectorElementCount();
@@ -6480,6 +6490,8 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
64806490
case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break;
64816491
case ISD::FLDEXP:
64826492
case ISD::FCOPYSIGN:
6493+
case ISD::LROUND:
6494+
case ISD::LLROUND:
64836495
case ISD::LRINT:
64846496
case ISD::LLRINT:
64856497
Res = WidenVecOp_UnrollVectorOp(N);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5436,6 +5436,8 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
54365436
case ISD::FCEIL:
54375437
case ISD::FROUND:
54385438
case ISD::FROUNDEVEN:
5439+
case ISD::LROUND:
5440+
case ISD::LLROUND:
54395441
case ISD::FRINT:
54405442
case ISD::LRINT:
54415443
case ISD::LLRINT:

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -774,8 +774,9 @@ void TargetLoweringBase::initActions() {
774774
setOperationAction(
775775
{ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG,
776776
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
777-
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::FTAN, ISD::FACOS,
778-
ISD::FASIN, ISD::FATAN, ISD::FCOSH, ISD::FSINH, ISD::FTANH},
777+
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::LROUND,
778+
ISD::LLROUND, ISD::FTAN, ISD::FACOS, ISD::FASIN, ISD::FATAN,
779+
ISD::FCOSH, ISD::FSINH, ISD::FTANH},
779780
VT, Expand);
780781

781782
// Constrained floating-point operations default to expand.

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