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[RISCV] Move RISCVInsertVSETVLI to after phi elimination
Split off from #70549, this patch moves RISCVInsertVSETVLI to after phi elimination where we exit SSA and need to move to LiveVariables. The motivation for splitting this off is to avoid the large scheduling diffs from moving completely to after regalloc, and instead focus on converting the pass to work on LiveIntervals. This limits the test diff to vsetvlis moving between csr and fsr instructions, due to RISCVInsertVSETVLI now taking place after RISCVInsertReadWriteCSR and RISCVInsertWriteVXRM. The two main changes required are updating VSETVLIInfo to store VNInfos instead of MachineInstrs, which allows us to still check for PHI defs in needVSETVLIPHI, and fixing up the live intervals of any AVL operands after inserting new instructions. On O3 the pass is inserted after the register coalescer, otherwise we end up with a bunch of COPYs around eliminated PHIs that trip up needVSETVLIPHI. Note that this manually fixes up the LiveIntervals instead of recomputing them as is currently done in #70549, since it seems to avoid most of the changes in spills and reloads that we were seeing. Specifically LIS->handleMove seemed to change the SlotIndex of instructions which might have affected regalloc. After this patch moving to post regalloc should be a matter of moving the pass in RISCVTargetMachines wihout any further changes to RISCVInsertVSETVLI itself. Co-authored-by: Piyou Chen <[email protected]> Co-authored-by: Luke Lau <[email protected]>
1 parent cd45bb2 commit e799314

29 files changed

+296
-258
lines changed

‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 152 additions & 96 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -543,7 +543,12 @@ void RISCVPassConfig::addPreRegAlloc() {
543543
addPass(createRISCVMergeBaseOffsetOptPass());
544544
addPass(createRISCVInsertReadWriteCSRPass());
545545
addPass(createRISCVInsertWriteVXRMPass());
546-
addPass(createRISCVInsertVSETVLIPass());
546+
// Run RISCVInsertVSETVLI after PHI elimination. On O1 and above do it after
547+
// register coalescing so needVSETVLIPHI doesn't need to look through COPYs.
548+
if (TM->getOptLevel() == CodeGenOptLevel::None)
549+
insertPass(&PHIEliminationID, createRISCVInsertVSETVLIPass());
550+
else
551+
insertPass(&RegisterCoalescerID, createRISCVInsertVSETVLIPass());
547552
}
548553

549554
void RISCVPassConfig::addFastRegAlloc() {

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,12 @@
4545
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4646
; CHECK-NEXT: Init Undef Pass
4747
; CHECK-NEXT: Eliminate PHI nodes for register allocation
48+
; CHECK-NEXT: MachineDominator Tree Construction
49+
; CHECK-NEXT: Slot index numbering
50+
; CHECK-NEXT: Live Interval Analysis
51+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
4852
; CHECK-NEXT: Two-Address instruction pass
4953
; CHECK-NEXT: Fast Register Allocator
50-
; CHECK-NEXT: MachineDominator Tree Construction
5154
; CHECK-NEXT: Slot index numbering
5255
; CHECK-NEXT: Live Interval Analysis
5356
; CHECK-NEXT: RISC-V Coalesce VSETVLI pass

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@
129129
; CHECK-NEXT: Slot index numbering
130130
; CHECK-NEXT: Live Interval Analysis
131131
; CHECK-NEXT: Register Coalescer
132+
; CHECK-NEXT: RISC-V Insert VSETVLI pass
132133
; CHECK-NEXT: Rename Disconnected Subregister Components
133134
; CHECK-NEXT: Machine Instruction Scheduler
134135
; CHECK-NEXT: Machine Block Frequency Analysis

‎llvm/test/CodeGen/RISCV/rvv/combine-vmv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,8 @@ define <vscale x 4 x i32> @vadd_undef(<vscale x 4 x i32> %a, <vscale x 4 x i32>
3636
define <vscale x 4 x i32> @vadd_same_passthru(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
3737
; CHECK-LABEL: vadd_same_passthru:
3838
; CHECK: # %bb.0:
39-
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
4039
; CHECK-NEXT: vmv2r.v v14, v8
40+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
4141
; CHECK-NEXT: vadd.vv v14, v10, v12
4242
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
4343
; CHECK-NEXT: vmv.v.v v8, v14

‎llvm/test/CodeGen/RISCV/rvv/concat-vectors-constant-stride.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,8 +149,8 @@ define void @constant_zero_stride(ptr %s, ptr %d) {
149149
; CHECK: # %bb.0:
150150
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
151151
; CHECK-NEXT: vle8.v v8, (a0)
152-
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
153152
; CHECK-NEXT: vmv1r.v v9, v8
153+
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
154154
; CHECK-NEXT: vslideup.vi v9, v8, 2
155155
; CHECK-NEXT: vse8.v v9, (a1)
156156
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -141,9 +141,9 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
141141
; SINK-NEXT: andi a4, a3, 1024
142142
; SINK-NEXT: xori a3, a4, 1024
143143
; SINK-NEXT: slli a5, a5, 1
144-
; SINK-NEXT: vsetvli a6, zero, e32, m2, ta, ma
145144
; SINK-NEXT: mv a6, a0
146145
; SINK-NEXT: mv a7, a3
146+
; SINK-NEXT: vsetvli t0, zero, e32, m2, ta, ma
147147
; SINK-NEXT: .LBB1_3: # %vector.body
148148
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
149149
; SINK-NEXT: vl2re32.v v8, (a6)
@@ -183,9 +183,9 @@ define void @sink_splat_add_scalable(ptr nocapture %a, i32 signext %x) {
183183
; DEFAULT-NEXT: andi a4, a3, 1024
184184
; DEFAULT-NEXT: xori a3, a4, 1024
185185
; DEFAULT-NEXT: slli a5, a5, 1
186-
; DEFAULT-NEXT: vsetvli a6, zero, e32, m2, ta, ma
187186
; DEFAULT-NEXT: mv a6, a0
188187
; DEFAULT-NEXT: mv a7, a3
188+
; DEFAULT-NEXT: vsetvli t0, zero, e32, m2, ta, ma
189189
; DEFAULT-NEXT: .LBB1_3: # %vector.body
190190
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
191191
; DEFAULT-NEXT: vl2re32.v v8, (a6)
@@ -459,9 +459,9 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
459459
; SINK-NEXT: addi a3, a2, -1
460460
; SINK-NEXT: andi a4, a3, 1024
461461
; SINK-NEXT: xori a3, a4, 1024
462-
; SINK-NEXT: vsetvli a5, zero, e32, m1, ta, ma
463462
; SINK-NEXT: mv a5, a0
464463
; SINK-NEXT: mv a6, a3
464+
; SINK-NEXT: vsetvli a7, zero, e32, m1, ta, ma
465465
; SINK-NEXT: .LBB4_3: # %vector.body
466466
; SINK-NEXT: # =>This Inner Loop Header: Depth=1
467467
; SINK-NEXT: vl1re32.v v8, (a5)
@@ -500,9 +500,9 @@ define void @sink_splat_fadd_scalable(ptr nocapture %a, float %x) {
500500
; DEFAULT-NEXT: addi a3, a2, -1
501501
; DEFAULT-NEXT: andi a4, a3, 1024
502502
; DEFAULT-NEXT: xori a3, a4, 1024
503-
; DEFAULT-NEXT: vsetvli a5, zero, e32, m1, ta, ma
504503
; DEFAULT-NEXT: mv a5, a0
505504
; DEFAULT-NEXT: mv a6, a3
505+
; DEFAULT-NEXT: vsetvli a7, zero, e32, m1, ta, ma
506506
; DEFAULT-NEXT: .LBB4_3: # %vector.body
507507
; DEFAULT-NEXT: # =>This Inner Loop Header: Depth=1
508508
; DEFAULT-NEXT: vl1re32.v v8, (a5)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1155,8 +1155,8 @@ define void @mulhu_v8i16(ptr %x) {
11551155
; CHECK-NEXT: vle16.v v8, (a0)
11561156
; CHECK-NEXT: vmv.v.i v9, 0
11571157
; CHECK-NEXT: lui a1, 1048568
1158-
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
11591158
; CHECK-NEXT: vmv.v.i v10, 0
1159+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
11601160
; CHECK-NEXT: vmv.s.x v10, a1
11611161
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
11621162
; CHECK-NEXT: vmv.v.i v11, 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12092,8 +12092,8 @@ define <32 x i8> @mgather_baseidx_v32i8(ptr %base, <32 x i8> %idxs, <32 x i1> %m
1209212092
; RV64V: # %bb.0:
1209312093
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
1209412094
; RV64V-NEXT: vsext.vf8 v16, v8
12095-
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
1209612095
; RV64V-NEXT: vmv1r.v v12, v10
12096+
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
1209712097
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
1209812098
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
1209912099
; RV64V-NEXT: vslidedown.vi v10, v10, 16

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -369,8 +369,8 @@ define <4 x i8> @vslide1up_4xi8_neg_incorrect_insert3(<4 x i8> %v, i8 %b) {
369369
define <2 x i8> @vslide1up_4xi8_neg_length_changing(<4 x i8> %v, i8 %b) {
370370
; CHECK-LABEL: vslide1up_4xi8_neg_length_changing:
371371
; CHECK: # %bb.0:
372-
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
373372
; CHECK-NEXT: vmv1r.v v9, v8
373+
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
374374
; CHECK-NEXT: vmv.s.x v9, a0
375375
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
376376
; CHECK-NEXT: vslideup.vi v9, v8, 1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,8 +168,8 @@ define void @strided_constant_0(ptr %x, ptr %z) {
168168
; CHECK: # %bb.0:
169169
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
170170
; CHECK-NEXT: vle16.v v8, (a0)
171-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
172171
; CHECK-NEXT: vmv1r.v v9, v8
172+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
173173
; CHECK-NEXT: vslideup.vi v9, v8, 4
174174
; CHECK-NEXT: vse16.v v9, (a1)
175175
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,8 +62,8 @@ define void @gather_masked(ptr noalias nocapture %A, ptr noalias nocapture reado
6262
; CHECK-NEXT: li a4, 5
6363
; CHECK-NEXT: .LBB1_1: # %vector.body
6464
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
65-
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, mu
6665
; CHECK-NEXT: vmv1r.v v9, v8
66+
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, mu
6767
; CHECK-NEXT: vlse8.v v9, (a1), a4, v0.t
6868
; CHECK-NEXT: vle8.v v10, (a0)
6969
; CHECK-NEXT: vadd.vv v9, v10, v9

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -394,14 +394,14 @@ define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 ze
394394
; CHECK-NEXT: # %bb.11:
395395
; CHECK-NEXT: li a1, 32
396396
; CHECK-NEXT: .LBB16_12:
397-
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
398397
; CHECK-NEXT: csrr a4, vlenb
399398
; CHECK-NEXT: li a5, 24
400399
; CHECK-NEXT: mul a4, a4, a5
401400
; CHECK-NEXT: add a4, sp, a4
402401
; CHECK-NEXT: addi a4, a4, 16
403402
; CHECK-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
404403
; CHECK-NEXT: vmv4r.v v24, v8
404+
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
405405
; CHECK-NEXT: csrr a4, vlenb
406406
; CHECK-NEXT: li a5, 56
407407
; CHECK-NEXT: mul a4, a4, a5

‎llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ define i32 @test(i32 %size, ptr %add.ptr, i64 %const) {
1515
; RV32-NEXT: .LBB0_1: # %for.body
1616
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
1717
; RV32-NEXT: vmv.s.x v9, zero
18-
; RV32-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
1918
; RV32-NEXT: vmv1r.v v10, v8
19+
; RV32-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
2020
; RV32-NEXT: vslideup.vx v10, v9, a2
2121
; RV32-NEXT: vsetivli zero, 8, e8, mf2, tu, ma
2222
; RV32-NEXT: vmv.s.x v10, a0
@@ -40,8 +40,8 @@ define i32 @test(i32 %size, ptr %add.ptr, i64 %const) {
4040
; RV64-NEXT: .LBB0_1: # %for.body
4141
; RV64-NEXT: # =>This Inner Loop Header: Depth=1
4242
; RV64-NEXT: vmv.s.x v9, zero
43-
; RV64-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
4443
; RV64-NEXT: vmv1r.v v10, v8
44+
; RV64-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
4545
; RV64-NEXT: vslideup.vx v10, v9, a2
4646
; RV64-NEXT: vsetivli zero, 8, e8, mf2, tu, ma
4747
; RV64-NEXT: vmv.s.x v10, a0

‎llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -479,11 +479,11 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) {
479479
; CHECK-V-NEXT: addi a0, sp, 16
480480
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
481481
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
482-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
483482
; CHECK-V-NEXT: csrr a0, vlenb
484483
; CHECK-V-NEXT: add a0, sp, a0
485484
; CHECK-V-NEXT: addi a0, a0, 16
486485
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
486+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
487487
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
488488
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
489489
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
@@ -640,11 +640,11 @@ define <4 x i32> @utesth_f16i32(<4 x half> %x) {
640640
; CHECK-V-NEXT: addi a0, sp, 16
641641
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
642642
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
643-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
644643
; CHECK-V-NEXT: csrr a0, vlenb
645644
; CHECK-V-NEXT: add a0, sp, a0
646645
; CHECK-V-NEXT: addi a0, a0, 16
647646
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
647+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
648648
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
649649
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
650650
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
@@ -811,11 +811,11 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
811811
; CHECK-V-NEXT: addi a0, sp, 16
812812
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
813813
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
814-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
815814
; CHECK-V-NEXT: csrr a0, vlenb
816815
; CHECK-V-NEXT: add a0, sp, a0
817816
; CHECK-V-NEXT: addi a0, a0, 16
818817
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
818+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
819819
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
820820
; CHECK-V-NEXT: li a0, -1
821821
; CHECK-V-NEXT: srli a0, a0, 32
@@ -3850,11 +3850,11 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
38503850
; CHECK-V-NEXT: addi a0, sp, 16
38513851
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
38523852
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
3853-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
38543853
; CHECK-V-NEXT: csrr a0, vlenb
38553854
; CHECK-V-NEXT: add a0, sp, a0
38563855
; CHECK-V-NEXT: addi a0, a0, 16
38573856
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
3857+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
38583858
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
38593859
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
38603860
; CHECK-V-NEXT: vnclip.wi v8, v10, 0
@@ -4009,11 +4009,11 @@ define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
40094009
; CHECK-V-NEXT: addi a0, sp, 16
40104010
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
40114011
; CHECK-V-NEXT: vslideup.vi v10, v8, 1
4012-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
40134012
; CHECK-V-NEXT: csrr a0, vlenb
40144013
; CHECK-V-NEXT: add a0, sp, a0
40154014
; CHECK-V-NEXT: addi a0, a0, 16
40164015
; CHECK-V-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
4016+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
40174017
; CHECK-V-NEXT: vslideup.vi v10, v8, 2
40184018
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
40194019
; CHECK-V-NEXT: vnclipu.wi v8, v10, 0
@@ -4179,11 +4179,11 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
41794179
; CHECK-V-NEXT: addi a0, sp, 16
41804180
; CHECK-V-NEXT: vl1r.v v9, (a0) # Unknown-size Folded Reload
41814181
; CHECK-V-NEXT: vslideup.vi v8, v9, 1
4182-
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
41834182
; CHECK-V-NEXT: csrr a0, vlenb
41844183
; CHECK-V-NEXT: add a0, sp, a0
41854184
; CHECK-V-NEXT: addi a0, a0, 16
41864185
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
4186+
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
41874187
; CHECK-V-NEXT: vslideup.vi v8, v10, 2
41884188
; CHECK-V-NEXT: li a0, -1
41894189
; CHECK-V-NEXT: srli a0, a0, 32

‎llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
2121
; SPILL-O0-NEXT: add a1, sp, a1
2222
; SPILL-O0-NEXT: addi a1, a1, 16
2323
; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
24-
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2524
; SPILL-O0-NEXT: # implicit-def: $v8
25+
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2626
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
2727
; SPILL-O0-NEXT: addi a0, sp, 16
2828
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
@@ -37,8 +37,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
3737
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
3838
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
3939
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
40-
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
4140
; SPILL-O0-NEXT: # implicit-def: $v8
41+
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
4242
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
4343
; SPILL-O0-NEXT: csrr a0, vlenb
4444
; SPILL-O0-NEXT: slli a0, a0, 1

‎llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
1313
; SPILL-O0-NEXT: csrr a2, vlenb
1414
; SPILL-O0-NEXT: slli a2, a2, 1
1515
; SPILL-O0-NEXT: sub sp, sp, a2
16-
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1716
; SPILL-O0-NEXT: # implicit-def: $v8_v9
17+
; SPILL-O0-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
1818
; SPILL-O0-NEXT: vlseg2e32.v v8, (a0)
1919
; SPILL-O0-NEXT: vmv1r.v v8, v9
2020
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -90,8 +90,8 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
9090
; SPILL-O0-NEXT: csrr a2, vlenb
9191
; SPILL-O0-NEXT: slli a2, a2, 1
9292
; SPILL-O0-NEXT: sub sp, sp, a2
93-
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, ta, ma
9493
; SPILL-O0-NEXT: # implicit-def: $v8_v9
94+
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m1, tu, ma
9595
; SPILL-O0-NEXT: vlseg2e32.v v8, (a0)
9696
; SPILL-O0-NEXT: vmv1r.v v8, v9
9797
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -167,8 +167,8 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
167167
; SPILL-O0-NEXT: csrr a2, vlenb
168168
; SPILL-O0-NEXT: slli a2, a2, 1
169169
; SPILL-O0-NEXT: sub sp, sp, a2
170-
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, ma
171170
; SPILL-O0-NEXT: # implicit-def: $v8m2_v10m2
171+
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, tu, ma
172172
; SPILL-O0-NEXT: vlseg2e32.v v8, (a0)
173173
; SPILL-O0-NEXT: vmv2r.v v8, v10
174174
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -247,8 +247,8 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
247247
; SPILL-O0-NEXT: csrr a2, vlenb
248248
; SPILL-O0-NEXT: slli a2, a2, 2
249249
; SPILL-O0-NEXT: sub sp, sp, a2
250-
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, ta, ma
251250
; SPILL-O0-NEXT: # implicit-def: $v8m4_v12m4
251+
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m4, tu, ma
252252
; SPILL-O0-NEXT: vlseg2e32.v v8, (a0)
253253
; SPILL-O0-NEXT: vmv4r.v v8, v12
254254
; SPILL-O0-NEXT: addi a0, sp, 16
@@ -327,8 +327,8 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
327327
; SPILL-O0-NEXT: csrr a2, vlenb
328328
; SPILL-O0-NEXT: slli a2, a2, 1
329329
; SPILL-O0-NEXT: sub sp, sp, a2
330-
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, ta, ma
331330
; SPILL-O0-NEXT: # implicit-def: $v8m2_v10m2_v12m2
331+
; SPILL-O0-NEXT: vsetvli zero, a1, e32, m2, tu, ma
332332
; SPILL-O0-NEXT: vlseg3e32.v v8, (a0)
333333
; SPILL-O0-NEXT: vmv2r.v v8, v10
334334
; SPILL-O0-NEXT: addi a0, sp, 16

‎llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
2424
; SPILL-O0-NEXT: add a1, sp, a1
2525
; SPILL-O0-NEXT: addi a1, a1, 32
2626
; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
27-
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2827
; SPILL-O0-NEXT: # implicit-def: $v8
28+
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2929
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
3030
; SPILL-O0-NEXT: addi a0, sp, 32
3131
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
@@ -40,8 +40,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
4040
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
4141
; SPILL-O0-NEXT: # kill: def $x11 killed $x10
4242
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
43-
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
4443
; SPILL-O0-NEXT: # implicit-def: $v8
44+
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
4545
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
4646
; SPILL-O0-NEXT: csrr a0, vlenb
4747
; SPILL-O0-NEXT: slli a0, a0, 1

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